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2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)最新文献

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ANYSYS chip-level and wafer-level simulation on semiconductor process development — Yu-Chih Chang ANYSYS在半导体制程发展上的片级与晶圆级模拟-张玉志
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089101
Chimin Chen, Yung-tai Hung, T. Luoh, Tahone Yang, Kuang-Chao Chen
{"title":"ANYSYS chip-level and wafer-level simulation on semiconductor process development — Yu-Chih Chang","authors":"Chimin Chen, Yung-tai Hung, T. Luoh, Tahone Yang, Kuang-Chao Chen","doi":"10.23919/ISSM.2017.8089101","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089101","url":null,"abstract":"Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal grain size behavior influence the BEOL leakage electrical properties; different design layout causes stress concentration issue, and different collapsed behavior induced by surface tension after wet strip. The wafer-level macro-structure simulation demonstrates that different pattern density of design will affect bow height performance in whole wafer. By means of ANSYS analysis, we can achieve more experiments or DOE splits by perdition simulation instead of real wafers and experiments. Thus, we can save the cost and achieve the time-to market requirement during product development.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132325325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Particle removal efficiency evaluation of filters in high temperature IPA 高温IPA中过滤器的颗粒去除效率评价
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089096
T. Takakura, S. Daikoku, S. Tsuzuki
{"title":"Particle removal efficiency evaluation of filters in high temperature IPA","authors":"T. Takakura, S. Daikoku, S. Tsuzuki","doi":"10.23919/ISSM.2017.8089096","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089096","url":null,"abstract":"The need of isopropyl alcohol (IPA) for wafer drying has been increasing in the semiconductor industry, because the structure of semiconductor devices is getting more complicated and IPA drying is more preferable to avoid pattern disruption of complicated device structure. Also, as the feature size of the semiconductor devices continuously decreasing, the cleanliness level of IPA needs to be further improved. Filtration is an indispensable technology to control the cleanliness, and more and more filters with finer removal rating are now being used to achieve the required cleanliness level.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123334535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A promising solution to reduce plasma induced damage (PID) of high density plasma (HDP) oxide without sacrificing the gap-fill and throughput performance — Chin-Tsan Yeh 减少高密度等离子体(HDP)氧化物的等离子体诱导损伤(PID)而不牺牲间隙填充和吞吐量性能的一种有前途的解决方案- chintsan Yeh
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089094
Chia-Sheng Yu, Ying-Tso Chen, Y. Shih, Chih-Yuan Lu
{"title":"A promising solution to reduce plasma induced damage (PID) of high density plasma (HDP) oxide without sacrificing the gap-fill and throughput performance — Chin-Tsan Yeh","authors":"Chia-Sheng Yu, Ying-Tso Chen, Y. Shih, Chih-Yuan Lu","doi":"10.23919/ISSM.2017.8089094","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089094","url":null,"abstract":"Plasma induced damage (PID) during high density plasma (HDP) chemical vapor deposition (CVD) deposition is a challenge for fabricating metal oxide semiconductor field effect transistors (MOSFETs). In this paper, reducing the plasma-induced damage to the thin gate oxides during inter-metal dielectric (IMD) gap-fill process is investigated. Applying in-situ silicon-rich oxide (SRO) or silicon oxy-nitride (SiON) before HDP oxide deposition is found capable of improving plasma damage. Blocking of ultraviolet (UV) light during HDP by SRO or SiON is believed the main reason for damage improvement. However, we report that only in-situ SRO can provide necessary gap-fill performance and good process throughput.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"773 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116413433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic scheduling of product-mix production systems of MTS and MTO MTS和MTO混合产品生产系统的动态调度
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089090
S. Arima, Yutong Zhang, Yutaka Akiyama, Yuri Ishizaki
{"title":"Dynamic scheduling of product-mix production systems of MTS and MTO","authors":"S. Arima, Yutong Zhang, Yutaka Akiyama, Yuri Ishizaki","doi":"10.23919/ISSM.2017.8089090","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089090","url":null,"abstract":"This paper discussed real-time solutions to product-mix scheduling problems (PMSPs) when a loading or a capacity of Fab are dynamically changing. The objective is that maximization of the resource utilization while keeping a due date and Q-time restrictions of every production lot. Particularly, two methods, P3D (Pseudo-Periodically Priority Dispatching) and the Palmer, are introduced for Make-to-Stock (MTS) and Make-to-Order (MTO) productions. After P3D's capabilities and limits about using demand forecasting are discussed, we newly introduced EDD-Palmer dispatching for product-mix MTO production for a case the demand prediction is difficult. The EDD-Palmer method evaluated for an actual wafer test process by comparing with EDD and EDD-CDS methods. This paper was concentrated in an optimal work leveling and dispatching of MTO WIPs.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131045239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Device scaling vs. process control scaling: Advanced sensorization closes the gap — Alan Weber 设备缩放vs过程控制缩放:先进的传感器缩小了差距- Alan Weber
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089091
Boyd Finlay, M. Reath, Jack Downey, C. Reeves, Jeff Wood, P. Minton, Niels Rackwitz, Eric Warren, Brian Conerny, Mohamed Elmrabet, R. Bunkofske
{"title":"Device scaling vs. process control scaling: Advanced sensorization closes the gap — Alan Weber","authors":"Boyd Finlay, M. Reath, Jack Downey, C. Reeves, Jeff Wood, P. Minton, Niels Rackwitz, Eric Warren, Brian Conerny, Mohamed Elmrabet, R. Bunkofske","doi":"10.23919/ISSM.2017.8089091","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089091","url":null,"abstract":"The rapid pace of device scaling in recent years has outrun the ability of today's generation of equipment control systems to keep up. New device architectures and the materials and processes used to realize them create sources of variability that require better techniques for real-time sensing, filtering, detection, and response. This is not simply a question of faster data collection of the existing equipment variables. In many cases, the data needed to accurately determine the real-time process conditions are not even available in the equipment, so the traditional time-based techniques and endpoint detection methods for controlling recipe execution are not sufficients rather, these advanced processes are effectively “flying blind.” GLOBALFOUNDRIES, a long-time leader in equipment automation and process control, has addressed these issues by integrating specialty sensors into the broader control environment, and shares highlights of their experience for a number of specific process areas in this presentation. It also covers techniques for leveraging today's data collection standards to streamline the integration process, and concludes with a list of suggestions for future equipment control design that deliver the required capabilities more effectively to support the next stages of process evolution.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130661898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Real-Time shceduling of HMLV productions using the optimum production cycle extended by ATSP solver 利用ATSP求解器扩展的最优生产周期实现HMLV生产的实时调度
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089103
S. Arima, Huizhen Bu, Yi-fang Wang, Yuri Ishizaki
{"title":"Real-Time shceduling of HMLV productions using the optimum production cycle extended by ATSP solver","authors":"S. Arima, Huizhen Bu, Yi-fang Wang, Yuri Ishizaki","doi":"10.23919/ISSM.2017.8089103","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089103","url":null,"abstract":"This paper discussed high-speed production scheduling for a high-mix low-volume (HMLV) production. A semiconductor wafer test process or assembly lines of electronic components are typical HMLV production systems in which several hundred products are produced in the same machine group at the same term (Week/Day). To improve the computational speed of Optimum Production Cycle (OPC) method for HMLV scheduling, the Miller-Tucker-Zemlin formulation of the Asymmetric Traveling Salesman Problem (ATSP) is used to find a cycle of minimum setup time in real-time. As the result of performance evaluations in an actual wafer test process, the computational time was about 10 seconds even in case that 16 product types and a reentrant step share the same machine. In addition, the proposed method improved the utilization of the machine group and due-date violations by 3% and 20.5% respectively.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132620823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Resolution of die chippings thru determination of occur and escape cause at automatic optical inspection process — Wiljelm Carl K. Olalia 通过测定自动光学检测过程中发生和脱落的原因来解决模屑问题。威廉·卡尔·k·奥拉利亚
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089100
Leo Angelo D. Oabel, Glenn T. Placido
{"title":"Resolution of die chippings thru determination of occur and escape cause at automatic optical inspection process — Wiljelm Carl K. Olalia","authors":"Leo Angelo D. Oabel, Glenn T. Placido","doi":"10.23919/ISSM.2017.8089100","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089100","url":null,"abstract":"At Wafer Level Chip Scale Package, Every Sawn Wafers underwent Automatic Optical Inspection to ensure that all Dice affected by Mechanical Defect specifically Chippings will be screened-out effectively. An average of 151 defect per million of Chippings has been effectively screen-out at AOI process from WW07'15 to WW32'15.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125876067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer pattern classification and auto disposition by machine learning — James Lin 基于机器学习的晶圆模式分类和自动配置- James Lin
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089084
J. Kung, P. Cheng, Austin Hwu, Chuang Tse Wang, Y. Hsu
{"title":"Wafer pattern classification and auto disposition by machine learning — James Lin","authors":"J. Kung, P. Cheng, Austin Hwu, Chuang Tse Wang, Y. Hsu","doi":"10.23919/ISSM.2017.8089084","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089084","url":null,"abstract":"In order to increase bad wafer detection rate and reduce engineer trouble-shooting efforts, this work reports a combination of machine learning techniques to decode and extract the wafer map information from tool log via text mining, transform to useful virtual wafer images by image processing, auto wafer pattern classification by deep learning, and perform auto disposition (scrap, rework, add inspection, or waive) by flow chart based decision rules. 70% hold time can be reduced for certain hold codes, so that the engineers can focus on more valuable jobs rather than trouble-shooting.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120975451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Base on bias and process capability index monitoring mechanism to improve tool consistency 基于偏置和工艺能力指标的监控机制，提高刀具一致性
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089092
Tzu-Ting Wang, Ya-Juan Chan, Ching-Wen Chung, Wei-Fu Chang
{"title":"Base on bias and process capability index monitoring mechanism to improve tool consistency","authors":"Tzu-Ting Wang, Ya-Juan Chan, Ching-Wen Chung, Wei-Fu Chang","doi":"10.23919/ISSM.2017.8089092","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089092","url":null,"abstract":"The monitoring mechanism uses in-line data which is conservative stratification and grouping to calculation %Bias. (%Bias=bias/process variation.) It represents tools are significant difference when %Bias>10% referring to MSA 2nd manual. As each tool is too stable, the influence of variation would be so sensitive, and the mechanism would be too strict. We developed if we combined %Bias criteria of MSA 2nd manual and Cpk monitor in order to solve the sensitive variation of the stable process. Therefore, this mechanism adds Cpk criterion. Due to the method focuses on tools consistency, the Ca formula is made an amendment to measure the degree between difference tools. In general, the criterion of Cpk is 1.67 that means process capability is capable. In the mechanism, the criterion of Cpk is tightened to 1.83. This paper discusses an inline monitoring mechanism to control tools consistency. We use Analysis of variance (ANOVA) test to prove the bias of tools that needs to improve. Therefore, we combined %Bias and Cpk to monitor in our mechanism. After improving the mechanism, it could solve the lack of the past mechanism. Finally, the mechanism can be immediate, comprehensive and effective to control and meet quality requirements.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An universal method to optimize shrunken distance of the step plate Tseng, Yun-Chieh 一种优化台阶板收缩距离的通用方法曾云杰
2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI: 10.23919/ISSM.2017.8089107
Chien-Hui Lu, Chien-Jung Chiu
{"title":"An universal method to optimize shrunken distance of the step plate Tseng, Yun-Chieh","authors":"Chien-Hui Lu, Chien-Jung Chiu","doi":"10.23919/ISSM.2017.8089107","DOIUrl":"https://doi.org/10.23919/ISSM.2017.8089107","url":null,"abstract":"In PVD (Physical Vapor Deposition) process, this study mainly exhibits an innovatively designing approach of thin film micro-control which the Dummy Plate of Step type and the proportional of step structure (h/d) were optimized to attain reasonable Guard band. The optimized approach can effectively reduce the film deposition to avoid shell-like defect and significantly improve the effect of the crystal defect on the wafer backside.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115338924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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