2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

Performance bound analysis of analog circuits considering process variations 考虑工艺变化的模拟电路性能界分析

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2012-03-09 DOI: 10.1109/ASPDAC.2012.6165011

Xuexin Liu, S. Tan, Zhigang Hao, G. Shi

引用次数: 19

Universal logic modules based on double-gate carbon nanotube transistors 基于双栅碳纳米管晶体管的通用逻辑模块

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024921

Andrew Zukoski, Xuebei Yang, K. Mohanram

{"title":"Universal logic modules based on double-gate carbon nanotube transistors","authors":"Andrew Zukoski, Xuebei Yang, K. Mohanram","doi":"10.1145/2024724.2024921","DOIUrl":"https://doi.org/10.1145/2024724.2024921","url":null,"abstract":"Double-gate carbon nanotube field-effect transistors (DG-CNTFETs) can be controlled in the field to be either n-type or p-type through an extra polarity gate. This results in an embedded XOR behavior, which has inspired several novel circuit designs and architectures. This work makes the following contributions. First, we propose an accurate and efficient semi-classical modeling approach to realize the first SPICE-compatible model for circuit design and optimization of DG-CNTFETs. Second, we design and optimize universal logic modules (ULMs) in two circuit styles based on DG-CNTFETs. The proposed ULMs can leverage the full potential of the embedded XOR through the FPGA-centric lookup table optimization flow. Further, we demonstrate that DG-CNTFET ULMs in the double pass-transistor logic style, which inherently produces dual-rail outputs with balanced delay, are faster than DG-CNTFET circuits in the conventional single-rail static logic style that relies on explicit input inversion. On average across 12 benchmarks, the proposed dual-rail ULMs outperform the best DG-CNTFET fabrics based on tiling patterns by 37%, 12%, and 33% in area, delay, and total power, respectively.","PeriodicalId":275305,"journal":{"name":"2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125150415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Global convergence analysis of mixed-signal systems 混合信号系统的全局收敛分析

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024841

Sangho Youn, Jaeha Kim, M. Horowitz

引用次数: 12

Extracting behavior and dynamically generated hierarchy from SystemC models 从SystemC模型中提取行为和动态生成的层次结构

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024810

Harry Broeders, R. V. Leuken

{"title":"Extracting behavior and dynamically generated hierarchy from SystemC models","authors":"Harry Broeders, R. V. Leuken","doi":"10.1145/2024724.2024810","DOIUrl":"https://doi.org/10.1145/2024724.2024810","url":null,"abstract":"We present a novel approach to extract the dynamically generated module hierarchy and its behavior from a SystemC model. SystemC is a popular modeling language which can be used to specify systems at a high ab]ion level. The module hierarchy of a SystemC model is dynamically constructed during the execution of the elaboration phase of the model. This means that a system designer can build regular structures using loops and conditional statements. Currently, most SystemC tools can not cope with SystemC models for which the module hierarchy depends on dynamic parameters. In our approach this hierarchical information is retrieved by controlling and monitoring the executing of the elaboration phase of the model using a GDB debugger. Thereafter, the behavioral information is retrieved by using a GCC plug-in. This plug-in produces ab] syntax trees in static single assignment form. This behavioral information is linked with the hierarchical information. Our approach is completely non-intrusive. The SystemC model and the SystemC reference implementation can be used without any modification. We have implemented our approach in a SystemC front-end called SHaBE (SystemC Hierarchy and Behavior Extractor). This front-end facilitates the development of future SystemC visualization, debugging, static verification, and synthesis tools.","PeriodicalId":275305,"journal":{"name":"2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114576246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification 利用无模型强化学习和贝叶斯分类，得出接近最优的电源管理策略

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024735

Yanzhi Wang, Q. Xie, A. Ammari, Massoud Pedram

{"title":"Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification","authors":"Yanzhi Wang, Q. Xie, A. Ammari, Massoud Pedram","doi":"10.1145/2024724.2024735","DOIUrl":"https://doi.org/10.1145/2024724.2024735","url":null,"abstract":"To cope with the variations and uncertainties that emanate from hardware and application characteristics, dynamic power management (DPM) frameworks must be able to learn about the system inputs and environment and adjust the power management policy on the fly. In this paper we present an online adaptive DPM technique based on model-free reinforcement learning (RL), which is commonly used to control stochastic dynamical systems. In particular, we employ temporal difference learning for semi-Markov decision process (SMDP) for the model-free RL. In addition a novel workload predictor based on an online Bayes classifier is presented to provide effective estimates of the workload states for the RL algorithm. In this DPM framework, power and latency tradeoffs can be precisely controlled based on a user-defined parameter. Experiments show that amount of average power saving (without any increase in the latency) is up to 16.7% compared to a reference expert-based approach. Alternatively, the per-request latency reduction without any power consumption increase is up to 28.6% compared to the expert-based approach.","PeriodicalId":275305,"journal":{"name":"2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 62

AENEID: A generic lithography-friendly detailed router based on post-RET data learning and hotspot detection AENEID:基于后ret数据学习和热点检测的通用光刻友好详细路由器

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024902

Duo Ding, Jhih-Rong Gao, Kun Yuan, D. Pan

引用次数: 23

Customer-aware task allocation and scheduling for multi-mode MPSoCs 基于客户感知的多模式mpsoc任务分配与调度

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024816

Lin Huang, Rong Ye, Q. Xu

引用次数: 12

Self-aligned double patterning decomposition for overlay minimization and hot spot detection 自对准双图案分解用于覆盖最小化和热点检测

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024741

Hongbo Zhang, Yuelin Du, Martin D. F. Wong, R. Topaloglu

引用次数: 44

TSV-aware analytical placement for 3D IC designs 三维集成电路设计的tsv感知分析放置

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024875

Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov

{"title":"TSV-aware analytical placement for 3D IC designs","authors":"Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov","doi":"10.1145/2024724.2024875","DOIUrl":"https://doi.org/10.1145/2024724.2024875","url":null,"abstract":"Through-silicon vias (TSVs) are required for transmitting signals among different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3D IC placement. Unlike most published 3D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3D cell placement algorithm which can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: (1) 3D analytical global placement with density optimization and whitespace reservation for TSVs, (2) TSV insertion and TSV-aware legalization, and (3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average wirelength model, giving the first model in the literature that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Further, 3D routing can easily be accomplished by traditional 2D routers since the physical positions of TSVs are determined during placement. Compared with state-of-the-art 3D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.","PeriodicalId":275305,"journal":{"name":"2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 93

Dynamic effort scaling: Managing the quality-efficiency tradeoff 动态工作量缩放:管理质量-效率的权衡

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2011-06-05 DOI: 10.1145/2024724.2024863

V. K. Chippa, A. Raghunathan, K. Roy, S. Chakradhar

{"title":"Dynamic effort scaling: Managing the quality-efficiency tradeoff","authors":"V. K. Chippa, A. Raghunathan, K. Roy, S. Chakradhar","doi":"10.1145/2024724.2024863","DOIUrl":"https://doi.org/10.1145/2024724.2024863","url":null,"abstract":"Several recently proposed design techniques leverage the inherent error resilience of applications for improved efficiency (energy or performance). Hardware and software systems that are thus designed may be viewed as “scalable effort systems”, since they offer the capability to modulate the effort that they expend towards computation, thereby allowing for tradeoffs between output quality and efficiency. We propose the concept of Dynamic Effort Scaling (DES), which refers to dynamic management of the control knobs that are exposed by scalable effort systems. We argue the need for DES by observing that the degree of resilience often varies significantly across applications, across datasets, and even within a dataset. We propose a general conceptual framework for DES by formulating it as a feedback control problem, wherein the scaling mechanisms are regulated with the goal of maintaining output quality within a certain specified limit. We present an implementation of Dynamic Effort Scaling in the context of a scalable-effort processor for Support Vector Machines, and evaluate it under various application scenarios and data sets. Our results clearly demonstrate the benefits of the proposed approach — statically setting the scaling mechanisms leads to either significant error overshoot or significant opportunities for energy savings left on the table unexploited. In contrast, DES is able to effectively regulate the output quality while maximally exploiting the time-varying resiliency in the workload.","PeriodicalId":275305,"journal":{"name":"2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123990755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 53