2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)最新文献_第7页

Batch Sequential Black-box Optimization with Embedding Alignment Cells for Logic Synthesis 逻辑合成中嵌入对齐单元的批量顺序黑盒优化

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549363

Chang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, M. Yuan, Jianye Hao

{"title":"Batch Sequential Black-box Optimization with Embedding Alignment Cells for Logic Synthesis","authors":"Chang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, M. Yuan, Jianye Hao","doi":"10.1145/3508352.3549363","DOIUrl":"https://doi.org/10.1145/3508352.3549363","url":null,"abstract":"During the logic synthesis flow of EDA, a sequence of graph transformation operators are applied to the circuits so that the Quality of Results (QoR) of the circuits highly depends on the chosen operators and their specific parameters in the sequence, making the search space operator-dependent and increasingly exponential. In this paper, we formulate the logic synthesis design space exploration as a conditional sequence optimization problem, where at each transformation step, an optimization operator is selected and its corresponding parameters are decided. To solve this problem, we propose a novel sequential black-box optimization approach without human intervention: 1) Due to the conditional and sequential structure of operator sequence with variable length, we build an embedding alignment cells based recurrent neural network as a surrogate model to estimate the QoR of the logic synthesis flow with historical data. 2) With the surrogate model, we construct acquisition function to balance exploration and exploitation with respect to each metric of the QoR. 3) We use multi-objective optimization algorithm to find the Pareto front of the acquisition functions, along which a batch of sequences, consisting of parameterized operators, are (randomly) selected to users for evaluation under the budget of computing resource. We repeat the above three steps until convergence or time limit. Experimental results on public EPFL benchmarks demonstrate the superiority of our approach over the expert-crafted optimization flows and other machine learning based methods. Compared to resyn2, we achieve 11.8% LUT-6 count descent improvements without sacrificing level values.","PeriodicalId":270592,"journal":{"name":"2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","volume":"490 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115305273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A High-precision Stochastic Solver for Steady-state Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions 具有傅里叶传热罗宾边界条件的稳态热分析高精度随机求解器

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549457

L. Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng

引用次数: 0

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration GIA:用于敏捷芯片集成的可重用通用中间层体系结构

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549464

Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li

{"title":"GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration","authors":"Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li","doi":"10.1145/3508352.3549464","DOIUrl":"https://doi.org/10.1145/3508352.3549464","url":null,"abstract":"2.5D chiplet technology is gaining popularity for the eﬃciency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered an ideal option for agile silicon system design by mitigating the huge design, verification, and manufacturing overhead of monolithic SoCs. Although it significantly reduces development costs by chiplet reuse, the design and fabrication of interposers also introduce additional high non-recurring engineering (NRE) costs and development cycles which might be prohibitive for application-specific designs having low volume.To address this challenge, in this paper, we propose a reusable general interposer architecture (GIA) to amortize NRE costs and accelerate integration flows of interposers across different chiplet-based systems effectively. The proposed assembly-time configurable interposer architecture covers both active interposers and passive interposers considering diverse applications of 2.5D systems. The agile interposer integration is also facilitated by a novel end-to-end design automation framework to generate optimal system assembly configurations including the selection of chiplets, inter-chiplet network configuration, placement of chiplets, and mapping on GIA, which are specialized for the given target workload. The experimental results show that our proposed active GIA and passive GIA achieve 3.15x and 60.92x performance boost with 2.57x and 2.99x power saving over baselines respectively.","PeriodicalId":270592,"journal":{"name":"2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123251687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An Approach to Unlocking Cyclic Logic Locking - LOOPLock 2.0 一种解锁循环逻辑锁的方法——LOOPLock 2.0

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549461

Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang

引用次数: 1

INDENT: Incremental Online Decision Tree Training for Domain-Specific Systems-on-Chip 针对特定领域的片上系统的增量在线决策树训练

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549436

A. Krishnakumar, R. Marculescu, Ümit Y. Ogras

{"title":"INDENT: Incremental Online Decision Tree Training for Domain-Specific Systems-on-Chip","authors":"A. Krishnakumar, R. Marculescu, Ümit Y. Ogras","doi":"10.1145/3508352.3549436","DOIUrl":"https://doi.org/10.1145/3508352.3549436","url":null,"abstract":"The performance and energy efficiency potential of heterogeneous architectures has fueled domain-specific systems-on-chip (DSSoCs) that integrate general-purpose and domain-specialized hardware accelerators. Decision trees (DTs) perform high-quality, low-latency task scheduling to utilize the massive parallelism and heterogeneity in DSSoCs effectively. However, offline trained DT scheduling policies can quickly become ineffective when applications or hardware configurations change. There is a critical need for runtime techniques to train DTs incrementally without sacrificing accuracy since current training approaches have large memory and computational power requirements. To address this need, we propose INDENT, an incremental online DT framework to update the scheduling policy and adapt it to unseen scenarios. INDENT updates DT schedulers at runtime using only 1-8% of the original training data embedded during training. Thorough evaluations with hardware platforms and DSSoC simulators demonstrate that INDENT performs within 5% of a DT trained from scratch using the entire dataset and outperforms current state-of-the-art approaches.","PeriodicalId":270592,"journal":{"name":"2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliable Computing of ReRAM Based Compute-in-Memory Circuits for AI Edge Devices 基于ReRAM的AI边缘设备内存计算电路的可靠计算

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3561119

Meng-Fan Chang, Je-Ming Hung, Ping-Cheng Chen, Tai-Hao Wen

引用次数: 1

Securing Hardware through Reconfigurable Nano-structures (Invited Paper) 通过可重构纳米结构保护硬件(特邀论文)

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3561116

N. Kavand, A. Darjani, Shubham Rai, Akash Kumar

引用次数: 1

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks DCIM-GCN:有效加速图卷积网络的数字内存计算

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549465

Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang

引用次数: 1

An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration 基于mlir的系统级设计和硬件加速编译流程

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3549424

Nicolas Bohm Agostini, S. Curzel, Vinay C. Amatya, Cheng Tan, Marco Minutoli, Vito Giovanni Castellana, J. Manzano, D. Kaeli, Antonino Tumeo

{"title":"An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration","authors":"Nicolas Bohm Agostini, S. Curzel, Vinay C. Amatya, Cheng Tan, Marco Minutoli, Vito Giovanni Castellana, J. Manzano, D. Kaeli, Antonino Tumeo","doi":"10.1145/3508352.3549424","DOIUrl":"https://doi.org/10.1145/3508352.3549424","url":null,"abstract":"The generation of custom hardware accelerators for applications implemented within high-level productive programming frameworks requires considerable manual effort. To automate this process, we introduce SODA-OPT, a compiler tool that extends the MLIR infrastructure. SODA-OPT automatically searches, outlines, tiles, and pre-optimizes relevant code regions to generate high-quality accelerators through high-level synthesis. SODA-OPT can support any high-level programming framework and domain-specific language that interface with the MLIR infrastructure. By leveraging MLIR, SODA-OPT solves compiler optimization problems with specialized abstractions. Backend synthesis tools connect to SODA-OPT through progressive intermediate representation lowerings. SODA-OPT interfaces to a design space exploration engine to identify the combination of compiler optimization passes and options that provides high-performance generated designs for different backends and targets. We demonstrate the practical applicability of the compilation flow by exploring the automatic generation of accelerators for deep neural networks operators outlined at arbitrary granularity and by combining outlining with tiling on large convolution layers. Experimental results with kernels from the PolyBench benchmark show that our high-level optimizations improve execution delays of synthesized accelerators up to 60x. We also show that for the selected kernels, our solution outperforms the current of state-of-the art in more than 70% of the benchmarks and provides better average speedup in 55% of them. SODA-OPT is an open source project available at https://gitlab.pnnl.gov/sodalite/soda-opt.","PeriodicalId":270592,"journal":{"name":"2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections 2022年ICCAD CAD竞赛题目B: D2D垂直连接的3D布局

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) Pub Date : 2022-10-29 DOI: 10.1145/3508352.3561108

Kai-Shun Hu, I-Jye Lin, Yu-Hui Huang, Hao-Yu Chi, Yi-Hsuan Wu, Cindy Chin-Fang Shen

引用次数: 4