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Int. J. High Speed Comput.最新文献

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Optimization of Reciprocals and Square Roots on the i860 Microprocessor i860微处理器上往复和平方根的优化
Int. J. High Speed Comput. Pub Date : 1996-03-01 DOI: 10.1142/S0129053396000057
R. Sinclair
{"title":"Optimization of Reciprocals and Square Roots on the i860 Microprocessor","authors":"R. Sinclair","doi":"10.1142/S0129053396000057","DOIUrl":"https://doi.org/10.1142/S0129053396000057","url":null,"abstract":"Reciprocal and reciprocal square root operations are partially supported by the i860 floating point unit, whereas square roots are not. We point out the reasons for this, and its consequences for the optimization of code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials. We conclude that code which can be optimized to explicitly combine reciprocals and square roots in the form of reciprocal square roots can attain significantly higher performance, and that assembly language coding of such operations can make the greatest use of the hardware by calculating only to the accuracy required, which may be less than single precision.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"470 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124432731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Complex Dynamics of a Simple Stock Market Model 一个简单股票市场模型的复杂动态
Int. J. High Speed Comput. Pub Date : 1996-03-01 DOI: 10.1142/S0129053396000082
Moshe Levy, N. Persky, S. Solomon
{"title":"The Complex Dynamics of a Simple Stock Market Model","authors":"Moshe Levy, N. Persky, S. Solomon","doi":"10.1142/S0129053396000082","DOIUrl":"https://doi.org/10.1142/S0129053396000082","url":null,"abstract":"We formulate a microscopic model of the stock market and study the resulting macroscopic phenomena via simulation. In a market of homogeneous investors periodic booms and crashes in stock price are obtained, When there are two types of investors in the market, differing only in their memory spans, we observe sharp irregular transitions between eras where one population dominates the market and eras where the other population dominates. When the number of investor subgroups is three the market undergoes a dramatic qualitative change — it becomes complex. We show that complexity is an intrinsic property of the stock market. This suggests an alternative to the widely accepted but empirically questionable random walk hypothesis.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Hierarchical Decomposition: a Parallel Implementation of the Barnes-Hut Tree Algorithm 层次分解:Barnes-Hut树算法的并行实现
Int. J. High Speed Comput. Pub Date : 1996-03-01 DOI: 10.1142/S0129053396000021
G. Bhanot, J. Janak, R. Walkup, V. Sonnad
{"title":"Hierarchical Decomposition: a Parallel Implementation of the Barnes-Hut Tree Algorithm","authors":"G. Bhanot, J. Janak, R. Walkup, V. Sonnad","doi":"10.1142/S0129053396000021","DOIUrl":"https://doi.org/10.1142/S0129053396000021","url":null,"abstract":"Given the coordinates of N points in D dimensions, the Barnes-Hut tree algorithm produces an ordered list so that successive pairs in the sequence are nearest neighbors, sets of four form a cluster, sets of eight form a bigger cluster, and so on. We describe a parallel implementation of this algorithm on the IBM SP2 using Fortran 77 and MPI message-passing calls, and study its performance.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121333773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Routing Algorithm for k-Ary n-Cube Interconnection Networks 一种新的k-Ary n-Cube互连网络路由算法
Int. J. High Speed Comput. Pub Date : 1996-03-01 DOI: 10.1142/S0129053396000070
E. Demaine, S. Sampalli
{"title":"A Novel Routing Algorithm for k-Ary n-Cube Interconnection Networks","authors":"E. Demaine, S. Sampalli","doi":"10.1142/S0129053396000070","DOIUrl":"https://doi.org/10.1142/S0129053396000070","url":null,"abstract":"This paper proposes a novel routing algorithm, called the direction-first e-cube, for routing on k-ary n-cube interconnection networks. It is an adaptive, partially minimal algorithm based on the wormhole-routing strategy and effectively extends the basic e-cube technique. It has been proved by a set of theorems that the proposed algorithm is deadlock-, livelock- and starvation-free. In the absence of faults, the algorithm is fully minimal. Even in the presence of faults and network congestion, the number of extra hops required to route a message is minimal. The algorithm is also simple to implement, since it utilizes a small header node of 2 log2 n+n log2k+1 bits. Simulation results are given to validate the proposed algorithm.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115573287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Topological Feature Maps on Parallel Computers 并行计算机上的拓扑特征映射
Int. J. High Speed Comput. Pub Date : 1995-12-01 DOI: 10.1142/S0129053395000294
Tao Li, L. Tao
{"title":"Topological Feature Maps on Parallel Computers","authors":"Tao Li, L. Tao","doi":"10.1142/S0129053395000294","DOIUrl":"https://doi.org/10.1142/S0129053395000294","url":null,"abstract":"Analysis of skewed memory schemes for parallel implementation of Kohonen’s topological feature maps are presented in this paper. It is found that linear skewing is more general and more effective for this problem as compared with other memory skewing schemes. Implementations on parallel machines and performance results will also be presented.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133396488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient Image Processing Applications on the MasPAR Massively Parallel Computers MasPAR大规模并行计算机上的高效图像处理应用
Int. J. High Speed Comput. Pub Date : 1995-12-01 DOI: 10.1142/S0129053395000270
M. Hamdi, Y. Pan, K. W. Tong
{"title":"Efficient Image Processing Applications on the MasPAR Massively Parallel Computers","authors":"M. Hamdi, Y. Pan, K. W. Tong","doi":"10.1142/S0129053395000270","DOIUrl":"https://doi.org/10.1142/S0129053395000270","url":null,"abstract":"Image processing applications are suitable candidates for parallelism and have at least in part motivated the design and development of some of the pioneering massively parallel processing systems including the CLIP family, the DAP, the MPP and the GAPP. In this paper, we describe the implementation of various image processing algorithms on the MasPar massively parallel computer system. The suitability of the MasPar for solving image processing algorithms is demonstrated either by parallelizing the algorithms using successful known techniques and/or developing new techniques suitable for the MasPar architecture. We quantitatively evaluate the performance of MasPar in solving these problems. Then, we compare its performance to various related massively parallel architectures. It is shown that the MasPar system compares favorably to these architectures, and is able to execute many fundamental image processing applications in a time amenable to real-time processing. Thus, the MasPar seems to be a promising architecture for massively parallel real-time image processing applications.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116729986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Processor Allocation in Extended Hypercube Multiprocessor 扩展超立方体多处理器中的处理器分配
Int. J. High Speed Comput. Pub Date : 1995-12-01 DOI: 10.1142/S0129053395000269
Sumeet Ahuja, A. Sarje
{"title":"Processor Allocation in Extended Hypercube Multiprocessor","authors":"Sumeet Ahuja, A. Sarje","doi":"10.1142/S0129053395000269","DOIUrl":"https://doi.org/10.1142/S0129053395000269","url":null,"abstract":"Processor allocation is an important issue for efficient utilization of a multiprocessor system. Several well-known methods exist for processor allocation in the hypercube multiprocessor. Some disadvantages of the hypercube structure have been overcome in the Extended Hypercube. The paper attempts at showing how the processor allocation schemes of hypercube can be extended to the Extended Hypercube structure. Results of a simulation study are also provided.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131040091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Processor Element for a High Performance Massively Parallel SIMD System 高性能大规模并行SIMD系统的处理器元件设计
Int. J. High Speed Comput. Pub Date : 1995-09-01 DOI: 10.1142/S0129053395000208
D. Beal, C. Lambrinoudakis
{"title":"Design of a Processor Element for a High Performance Massively Parallel SIMD System","authors":"D. Beal, C. Lambrinoudakis","doi":"10.1142/S0129053395000208","DOIUrl":"https://doi.org/10.1142/S0129053395000208","url":null,"abstract":"This paper describes the architecture of the General Purpose with Floating Point support (GPFP) processing element, which uses the expansion of circuitry from VLSI advances to provide on-chip memory and cost-effective extra functionality. A major goal was to accelerate floating point arithmetic. This was combined with architectural aims of cost-effectiveness, achieving the floating-point capability from general-purpose units, and retaining the 1-bit manipulations available in the earlier generation. With a 50 MHz clock each PE is capable of 2.5 MegaFlops. Normalized to the same clock rate, the GPFP PE exceeds first generation PEs by far, namely the DAP by a factor of 50 and the MPP by a factor of 20, and also outperforms the recent MasPar design by a factor of four. A 32×32 GPFP array is capable of up to 2.5 GigaFlops and 6500 MIPS, on 32-bit additions. These speedups are obtained by architectural features rather than increased width of data-handling and are combined with parsimonious use of circuitry compatible with massively parallel fabrication. The GPFP also incorporates Reconfigurable Local Control (RLC), a technique that combines a considerable degree of local autonomy within PEs and microcode flexibility, giving the machine improved general-purpose programmability in addition to floating-point numerical performance.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124243645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault Tolerant Systolic Evaluation of Polynomials and Exponentials of Polynomials for equispaced Arguments Using Time Redundancy 基于时间冗余的均衡参数多项式和多项式指数的容错收缩求值
Int. J. High Speed Comput. Pub Date : 1995-09-01 DOI: 10.1142/S0129053395000191
M. Vijay
{"title":"Fault Tolerant Systolic Evaluation of Polynomials and Exponentials of Polynomials for equispaced Arguments Using Time Redundancy","authors":"M. Vijay","doi":"10.1142/S0129053395000191","DOIUrl":"https://doi.org/10.1142/S0129053395000191","url":null,"abstract":"Many applications which require high speed evaluation of polynomials and exponentials of polynomials can now be implemented in the hardware very efficiently because of the advances in VLSI technology. Several fast algorithms have been proposed in the recent past for the efficient evaluation of polynomials and exponentials of polynomials for equispaced arguments on uniprocessor systems. In this paper, we consider the problem of organizing this evaluation on VLSI chips in the form of systolic arrays. We present linear fault tolerant systolic arrays which can evaluate the polynomials and exponentials of polynomials of any degree for a large number of equispaced points. These organizations have the main advantage that the interconnections between the processing elements are very regular and simple, and hence are very appropriate for VLSI implementation.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulations of Interacting Many Body Systems Using P4 基于P4的多体系统交互仿真
Int. J. High Speed Comput. Pub Date : 1995-09-01 DOI: 10.1142/S012905339500018X
R. Scalettar, K. Runge, J. Correa, P. Lee, V. Oklobdzija, J. Vujic
{"title":"Simulations of Interacting Many Body Systems Using P4","authors":"R. Scalettar, K. Runge, J. Correa, P. Lee, V. Oklobdzija, J. Vujic","doi":"10.1142/S012905339500018X","DOIUrl":"https://doi.org/10.1142/S012905339500018X","url":null,"abstract":"Monte Carlo (MC) and Molecular Dynamics (MD) simulations are powerful tools for understanding the low temperature properties of systems of interacting electrons and phonons in a solid, including the phenomena of magnetism and superconductivity. When mobile electrons are studied, these simulations are currently limited to a few hundred particles, and also largely to “clean” systems where no defects are present. Therefore, more powerful machines and algorithms must be used to address many of the most important issues in the field. In this paper, we present results from using some simple implementations of the p4 parallel programming system on a variety of parallel architectures to conduct MC and MD simulations of one and two dimensional electron-phonon models.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128029307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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