Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis最新文献

Designing parameterized signal processing ips for high level synthesis in a model based design environment 在基于模型的设计环境中设计用于高级综合的参数化信号处理ip

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380493

S. Butt, L. Lavagno

{"title":"Designing parameterized signal processing ips for high level synthesis in a model based design environment","authors":"S. Butt, L. Lavagno","doi":"10.1145/2380445.2380493","DOIUrl":"https://doi.org/10.1145/2380445.2380493","url":null,"abstract":"Model based hardware/software synthesis can lead to fast and efficient embedded system implementations, by enabling quick design space exploration. High level hardware modeling and implementation can be accelerated by using functionally verified parameterized models that are optimized for high level hardware synthesis. Such models can be designed so that they can be easily integrated with a high level modeling environment, such as Simulink, and at the same time provide ample flexibility to perform design space exploration when mapped to hardware. During signal processing hardware design, the focus is mostly on the architectural representation (data parallelism, pipelining, memory access, etc.) to meet throughput requirement and on data path modeling to analyze the effects of quantization. In this paper we present our experience of modeling an FFT block that can be integrated with the Simulink model based design environment for simulation and verification, and later can be used to perform architectural design space exploration and hardware implementation with optimal data path selection. A key advantage of our model is that the very same bit-accurate C code is used for simulation and for high-level synthesis, because it has been written with both aspects in mind (while for software implementation either our code or the code provided by the Mathworks can be used equally well). To prove the feasibility of our proposed approach we synthesized our FFT for two DSP applications with very different performance and cost requirements, namely a frequency domain audio detector and a GPS acquisition algorithm, and compared it with existing manual implementations","PeriodicalId":268500,"journal":{"name":"Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124414355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Session details: Special session: synthesis of executable extra-functional system-level models for timing and power exploration 会议细节:特别会议:用于时序和功率探索的可执行的功能外系统级模型的综合

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/3250282

Kim Grüttner

引用次数: 0

DevScope: a nonintrusive and online power analysis tool for smartphone hardware components DevScope:智能手机硬件组件的非侵入式在线电源分析工具

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380502

Wonwoo Jung, C. Kang, Chanmin Yoon, Dongwon Kim, H. Cha

{"title":"DevScope: a nonintrusive and online power analysis tool for smartphone hardware components","authors":"Wonwoo Jung, C. Kang, Chanmin Yoon, Dongwon Kim, H. Cha","doi":"10.1145/2380445.2380502","DOIUrl":"https://doi.org/10.1145/2380445.2380502","url":null,"abstract":"Smartphone power modeling is an important technique for users, application developers, and hardware manufacturers to build energy-aware systems. Compared to traditional offline techniques that use external power measurement devices, the online approach uses a built-in BMU (Battery Monitoring Unit), which has the advantage of generating a dynamic power model. However, the very low update rate of a BMU is an issue for online power modeling. In this paper, we introduce an autonomous power modeling tool for smartphones called DevScope, which overcomes the limitations of BMU-based online power modeling. DevScope controls components according to the BMU update rate, and derives the component power model automatically by analyzing the changes of power state. With DevScope, we construct an online and automatic power modeling that reflects both the diversity of users' environments and smartphone hardware complexity. By evaluating the scheme with various smartphones and configurations, we show that DevScope, indeed, generates a flexible and accurate power model.","PeriodicalId":268500,"journal":{"name":"Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114427456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 134

Session details: System-level synthesis and optimization 会议细节:系统级综合和优化

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/3250284

B. Meyer

引用次数: 0

Knowledge-based design space exploration of wireless sensor networks 基于知识的无线传感器网络设计空间探索

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380484

P. Grassi, I. Beretta, V. Rana, David Atienza Alonso, D. Sciuto

{"title":"Knowledge-based design space exploration of wireless sensor networks","authors":"P. Grassi, I. Beretta, V. Rana, David Atienza Alonso, D. Sciuto","doi":"10.1145/2380445.2380484","DOIUrl":"https://doi.org/10.1145/2380445.2380484","url":null,"abstract":"The complexity of Wireless Sensor Networks (WSNs) has been constantly increasing over the last decade, and the necessity of efficient CAD tools has been growing accordingly. In fact, the size of the design space of a WSN has become large, and an exploration conducted by using semi-random algorithms (such as the popular genetic or simulated annealing algorithms) requires an unacceptable amount of time to converge due to the high number of parameters involved. To address this issue, in this paper we introduce a knowledge-based design space exploration algorithm for the WSN domain, which is based on a discrete-space Markov decision process (MDP). In order to enhance the performance of the proposed algorithm and to increase its scalability, we tailor the classical MDP approach to the specific aspects that characterize the WSN domain. We exploit domain-specific knowledge to choose the best node-level configuration in WSNs using slotted star topology in order to reduce the exploration time. The proposed approach has been tested on IEEE 802.15.4 star networks with various configurations of the number of nodes and their packet rates. Experimental results show that the proposed algorithm reduces the number of simulations required to converge, with respect to state-of-the-art algorithms (e.g., NSGA-II, PMA and MOSA), from 60 to 87%","PeriodicalId":268500,"journal":{"name":"Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127953421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Run-time resource management based on design space exploration 基于设计空间探索的运行时资源管理

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380530

C. Ykman-Couvreur, Philipp A. Hartmann, G. Palermo, Fabien Colas-Bigey, Laurent San

{"title":"Run-time resource management based on design space exploration","authors":"C. Ykman-Couvreur, Philipp A. Hartmann, G. Palermo, Fabien Colas-Bigey, Laurent San","doi":"10.1145/2380445.2380530","DOIUrl":"https://doi.org/10.1145/2380445.2380530","url":null,"abstract":"A main challenge in today's embedded system design is to find the perfect balance between performance and power consumption. This paper presents a run-time resource management framework for embedded heterogeneous multi-core platforms. It allows dynamic adaptation to changing application context and transparent optimization of the platform resource usage following a distributed and hierarchical approach. A Global Resource Manager (GRM) is running in parallel with the central manager of the application on the host processor of the platform. Each IP core of the platform can execute its own Local Resource Manager (LRM), and the GRM conforms to practices of each LRM. The operating points managed by the GRM are identified in a design-space exploration phase as a set of Pareto-optimal configurations of the application and their impacts with regards to the quality of experience, performance and energy consumption. The GRM has already been integrated in a POSIX version of an audio-driven video surveillance application in order to maximize its QoE parameters with respect to the battery duration and the energy budget of the platform, used to analyze the GRM efficiency.","PeriodicalId":268500,"journal":{"name":"Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132519009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Session details: Emulation of physical systems and design of wireless sensor networks 会议细节:物理系统仿真和无线传感器网络设计

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/3250273

P. Eles

引用次数: 0

A testbench specification language for SystemC verification 用于SystemC验证的测试台规范语言

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380499

G. D. Guglielmo, G. Pravadelli

{"title":"A testbench specification language for SystemC verification","authors":"G. D. Guglielmo, G. Pravadelli","doi":"10.1145/2380445.2380499","DOIUrl":"https://doi.org/10.1145/2380445.2380499","url":null,"abstract":"Testing of embedded systems, operating in the real environment, is generally performed by using an industrial test bench that stimulates the system through sensors and human-machine interfaces. The test bench provides the engineers with a set of tools for reproducing the environmental conditions which may affect the system. On the contrary, a different approach is adopted at the early stages of the design flow, when system level languages, like SystemC, are used to describe the functionality of the design. At this level, stimuli for testing the design are traditionally generated in a random or statistical way, which makes more difficult to capture well-specific behaviors of the considered environment, thus decreasing the effectiveness and the efficiency of the verification. This is particularly evident for dynamic assertion-based verification where, to avoid vacuous passes of assertions, stimuli must reflect specific scenarios to activate the assertions. In this work, we propose a graphical framework to automatically generate stimuli, particularly suited to be used for dynamic ABV of embedded SW. The framework relies on the definition of a Testbench Specification Language (TSL) that allows to formally capture the behavior of the real environment where embedded SW is intended to be executed, i.e., how input values evolve on time intervals. Then, the framework allows to automatically synthesize TSL descriptions into SystemC-based stimuli generators, which exploit and extend the functionality of the SystemC Verification Library.","PeriodicalId":268500,"journal":{"name":"Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126910572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Fast simulation of systems embedding VLIW processors 嵌入式VLIW处理器系统的快速仿真

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380472

Luc Michel, Nicolas Fournel, F. Pétrot

引用次数: 7

Synthesis of communication schedules for TTEthernet-based mixed-criticality systems 基于以太网的混合临界系统的通信调度综合

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis Pub Date : 2012-10-07 DOI: 10.1145/2380445.2380518

D. Tamas-Selicean, P. Pop, W. Steiner

{"title":"Synthesis of communication schedules for TTEthernet-based mixed-criticality systems","authors":"D. Tamas-Selicean, P. Pop, W. Steiner","doi":"10.1145/2380445.2380518","DOIUrl":"https://doi.org/10.1145/2380445.2380518","url":null,"abstract":"In this paper we are interested in safety-critical distributed systems, composed of heterogeneous processing elements interconnected using the TTEthernet protocol. We address hard real-time mixed-criticality applications, which may have different criticality levels, and we focus on the optimization of the communication configuration. TTEthernet integrates three types of traffic: Time-Triggered (TT) messages, Event-Triggered (ET) messages with bounded end-to-end delay, also called Rate Constrained (RC) messages, and Best-Effort (BE) messages, for which no timing guarantees are provided. TT messages are transmitted based on static schedule tables, and have the highest priority. RC messages are transmitted if there are no TT messages, and BE traffic has the lowest priority. TT and RC traffic can carry safety-critical messages, while BE messages are non-critical. Mixed-criticality tasks and messages can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. TTEthernet offers spatial separation for mixed-criticality messages through the concept of virtual links, and temporal separation, enforced through schedule tables for TT messages and bandwidth allocation for RC messages. Given the set of mixed-criticality messages in the system and the topology of the virtual links on which the messages are transmitted, we are interested to synthesize offline the static schedules for the TT messages, such that the deadlines for the TT and RC messages are satisfied, and the end-to-end delay of the RC traffic is minimized. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several benchmarks.","PeriodicalId":268500,"journal":{"name":"Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122327738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 96