2004 International Symposium on System-on-Chip, 2004. Proceedings.最新文献_第4页

A fully integrated low-IF DVB-T receiver architecture 完全集成的低中频DVB-T接收机架构

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411182

G. Andrijevic, H. Magnusson, Henrik Olsson

引用次数: 3

Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility 用于无线通信的特定于应用程序的指令集处理器(ASIP):设计、成本和能效与灵活性

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411050

H. Meyr

{"title":"Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility","authors":"H. Meyr","doi":"10.1109/ISSOC.2004.1411050","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411050","url":null,"abstract":"Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation. To meet conflicting goals such as energy efficiency and flexibility together with cost, time-to-market and reusability constraints a radically different, truly innovative architectural approach is necessary for SoCs applied to wireless communications. These future SoCs can be viewed as heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks (NoC). The success of the proposed MP-SoC is ultimately linked to the availability of an equally innovative system-level design (SLD) methodology together with the corresponding SLD tool suite. In this presentation, we address this innovative SLD design flow in the context of wireless communications. The focus of this presentation is primarily on one crucial aspect of this process: the spatial mapping of application tasks onto ASIPs.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124733974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementing a single-processor cellular modem on an SC1000-family core 在sc1000系列核心上实现单处理器蜂窝调制解调器

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411051

S. Angioni, F. Lazare

引用次数: 0

Estimation of a maximum bound of uncertain parameter fluctuations with applications to analogue IP-cores 不确定参数波动的最大界估计与模拟ip核的应用

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411176

H. Kadim

引用次数: 10

Reusable XGFT interconnect IP for network-on-chip implementations 用于片上网络实现的可重用XGFT互连IP

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411159

H. Kariniemi, J. Nurmi

{"title":"Reusable XGFT interconnect IP for network-on-chip implementations","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/ISSOC.2004.1411159","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411159","url":null,"abstract":"Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) IIP can be used as a single large block. It is especially usable on such SoC circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT HP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in network-on-chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Efficient barrier synchronization mechanism for emulated shared memory NOCs 模拟共享内存noc的高效屏障同步机制

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411139

M. Forsell

引用次数: 2

Design of a guaranteed throughput router for on-chip networks 片上网络中保证吞吐量路由器的设计

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411137

S. Sathe, D. Wiklund, Dake Liu

引用次数: 5

High speed and low power on-chip micro network circuit with differential transmission line 采用差分传输线的高速低功耗片上微网络电路

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411178

S. Gomi, K. Nakamura, Hiroyuki Ito, H. Sugita, K. Okada, K. Masu

引用次数: 2

Practical distributed simulation of a network of wireless terminals 实用的无线终端网络分布式仿真

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411144

Jouni Riihimäki, Petri Kukkala, E. Salminen, Marko Hännikäinen, Kimmo Kuusilinna, T. Hämäläinen

引用次数: 2

A scalable embedded DSP core for SoC applications 一个可扩展的嵌入式DSP核心的SoC应用

2004 International Symposium on System-on-Chip, 2004. Proceedings. Pub Date : 2004-11-16 DOI: 10.1109/ISSOC.2004.1411155

C. Panis, U. Hirnschrott, S. Farfeleder, A. Krall, G. Laure, W. Lazian, J. Nurmi

引用次数: 18