A scalable embedded DSP core for SoC applications

Abstract

Increasing system complexity of SoC (system-on-chip) and SiP (system-in-package) applications leads to the strong demand of platform based solutions. Software programmable embedded cores are required to provide flexibility to these platforms. Compared with dedicated hardware implementations the provided flexibility leads to increased silicon area and power dissipation, which is problematic for high volume products. This paper introduces xDSPcore, a scalable embedded DSP processor which allows to scale major architectural features to application specific requirements. Compatibility issues caused by different core versions are covered by the support of efficient programming in high-level languages like C, which is achieved by an optimizing C-compiler and by a compiler friendly core architecture. A particular core definition is specified by a XML based configuration file.