2019 IEEE International Solid- State Circuits Conference - (ISSCC)最新文献_第2页

27.5 A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications 27.5一种用于LTE-80MHz应用的91%效率的包络跟踪调制器，该调制器采用迟滞控制三电平开关稳压器和螺旋速率增强线性放大器

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-03-06 DOI: 10.1109/ISSCC.2019.8662305

Parisa Mahmoudidaryan, Debashis Mandal, B. Bakkaloglu, S. Kiaei

引用次数: 10

11.2 A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range 11.2具有1024个3电极伏安像素和93dB动态范围的CMOS生物传感器阵列

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-03-06 DOI: 10.1109/ISSCC.2019.8662507

Arun Manickam, Kae-Dyi You, Nicholas Wood, Lei Pei, Yang Liu, Rituraj Singh, N. Gamini, D. Shahrjerdi, R. Kuimelis, A. Hassibi

引用次数: 12

23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface 23.3用于下一代内存接口的3bit /2UI 27Gb/s PAM-3单端单端DFE

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-03-06 DOI: 10.1109/ISSCC.2019.8662462

Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim

{"title":"23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface","authors":"Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim","doi":"10.1109/ISSCC.2019.8662462","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662462","url":null,"abstract":"Bandwidths of memory interfaces have been increased tremendously to enable high-data throughput while maintaining single-ended signaling and the supply voltage of I/O has been scaled down. Due to the increasing interface bandwidth the required area and power consumption has increased as well, resulting in higher I/O circuit design costs [3]. A high-loss channel causes ISI, which in turn limits the maximum data rate. Therefore, complex equalizers are needed for compensation, resulting in additional power dissipation and area overhead. As the data sampling rate increases, the deterministic and random noises degrade the data sampling margin and further limit the bandwidth. To lessen the negative impact of high channel loss and to reduce the forwarded clock frequency, multi-level signaling, such as PAM-4, can be used, as shown in Fig. 23.3.1 [2]. While the voltage sense margin for PAM-4 is theoretically $frac{1}{3}$ of NRZ, in practice it is smaller due to simultaneous switching noise (SSN), crosstalk, and random noise in single-ended signaling. Eventually, the reduced voltage sense margin degrades the SNR, which causes a reduction in the BER. On the other hand, PAM-3’s voltage sense margin is ${textstyle frac {1}{2}}$ of NRZ’s. Duo-binary signaling is commonly used for PAM-3 signaling [1]. However, the pin efficiency and the forwarded clock frequency for duo-binary signaling is the same as for NRZ. In this paper, a 3b/2UI PAM-3 single-ended memory interface is proposed, with a pin efficiency of 150% and a reduced clock frequency, compared to NRZ signaling. To address PAM-3 equalizer inefficiencies a tri-level decision feedback equalizer (DFE) is implemented in the receiver (RX).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124588981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

1.1 Deep Learning Hardware: Past, Present, and Future 1.1深度学习硬件:过去、现在和未来

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-03-06 DOI: 10.1109/ISSCC.2019.8662396

Yann LeCun

引用次数: 89

22.4 A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS 22.4 A 27.8μW可承受30Vpp共模干扰的生物电位放大器，用于0.18μm CMOS双电极ECG记录

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-02-20 DOI: 10.1109/ISSCC.2019.8662373

Nahmil Koo, Seonghwan Cho

引用次数: 3

9.8 A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters 9.8一种具有嵌入式开关和双矢量变增益移相器的28GHz、20.3%、发射效率1.5°、相位误差波束形成前端集成电路

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-02-18 DOI: 10.1109/ISSCC.2019.8662512

Jinseok Park, Seungchan Lee, Dong-Ho Lee, Songcheol Hong

引用次数: 45

6.7 A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS 6.7 A 112Gb/s PAM-4电压型变送器，带有4抽头两步FFE和40nm CMOS自动相位对准技术

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-02-01 DOI: 10.1109/ISSCC.2019.8662361

Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, T. Shih

引用次数: 13

17.3 Hybrid System for Efficient LAE-CMOS Interfacing in Large-Scale Tactile-Sensing Skins via TFT-Based Compressed Sensing 17.3基于tft压缩传感的大规模触觉传感皮肤中高效LAE-CMOS接口混合系统

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-02-01 DOI: 10.1109/ISSCC.2019.8662442

L. E. Aygun, Prakhar Kumar, Zhiwu Zheng, Ting-Sheng Chen, S. Wagner, J. Sturm, N. Verma

{"title":"17.3 Hybrid System for Efficient LAE-CMOS Interfacing in Large-Scale Tactile-Sensing Skins via TFT-Based Compressed Sensing","authors":"L. E. Aygun, Prakhar Kumar, Zhiwu Zheng, Ting-Sheng Chen, S. Wagner, J. Sturm, N. Verma","doi":"10.1109/ISSCC.2019.8662442","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662442","url":null,"abstract":"Tactile sensing has wide-ranging applications, from intelligent surfaces to advanced robotics. Large-Area Electronics (LAE), based on low-temp. fabrication $(lt 200 ^{circ}mathrm {C})$ of thin films, presents distinct capabilities, due to compatibility with a broad range of materials (enabling diverse transducers), as well as large and flexible substrates and materials-deposition methods (enabling expansive and formfitting sensing arrays). However, low performance/energy-efficiency of LAE thin-film transistors (TFTs) necessitates hybrid systems, integrating Si-CMOS ICs for system functions (sensor readout/control, processing, etc.). Initial work shows that a primary challenge in hybrid systems is the large number of interfaces required between LAE and CMOS, particularly as the number of sensors scales [1], [2]. This paper presents a force-sensing system that exploits signal sparsity exhibited in many large-area tactile-sensing applications (e.g., detecting point damage/stress in structures [3]), to reduce interfacing complexity to the level of sparsity, rather than a level related to the number of sensors (e.g., [1]). This is achieved via compressed sensing (CS), enabling sensor-acquisition by simple switches, readily implemented using TFTs. While CS has previously been leveraged in a hybrid-system architecture targeting signal sampling-rate requirements [2], this system applies it for high spatial resolution in tactile sensing.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125183732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

10.1 An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors 10.1集成现场背景全系统精度监测(包括电流和电压传感器)的能量测量前端

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-02-01 DOI: 10.1109/ISSCC.2019.8662542

Seyed Danesh, W. Holland, J. Spalding, Michael Guidry, J. Hurwitz

{"title":"10.1 An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors","authors":"Seyed Danesh, W. Holland, J. Spalding, Michael Guidry, J. Hurwitz","doi":"10.1109/ISSCC.2019.8662542","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662542","url":null,"abstract":"Millions of utility electricity meters are deployed globally to determine billable energy consumption. These devices are factory calibrated, and then perform measurement without interruption over their lifetime. Once in the field their accuracy is unknown due to component aging and high voltage/current events [1]. Meters are periodically replaced as a preventive measure, leading to the unnecessary replacement of perfectly good meters while some inaccurate meters may remain in field. This paper presents an energy-measurement front-end that enables continuous background Condition Base Monitoring (CbM) over the lifetime of a meter. Crucially it monitors the performance of its voltage and current sensors, which are typically the largest sources of inaccuracy and drift. During normal operation, small test signals (“stimuli”), with adaptable but well-defined characteristics are injected into the sensors. Their amplitudes at the front-end’s output are then extracted to determine the gain accuracy of the full signal chain. In order to do this, the system must meet 3 main challenges. First, it must be able to generate and inject highly stable and accurate stimuli signals into the sensors. Second, it must have a wide dynamic range in order to accurately extract the stimuli in the presence of unknown and significantly larger load signals. Third, it must incorporate all the digital signal processing involved with stimuli signal selection, extraction and removal. This paper describes the circuit techniques used to address the first two challenges.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123457994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

10.3 A 0.12mm2 Wien-Bridge Temperature Sensor with 0.1°C (3σ) Inaccuracy from -40°C to 180°C 10.3 A 0.12mm2温桥温度传感器，0.1°C (3σ)误差范围为-40°C至180°C

2019 IEEE International Solid- State Circuits Conference - (ISSCC) Pub Date : 2019-02-01 DOI: 10.1109/ISSCC.2019.8662457

S. Pan, Cagri Gurleyuk, Matheus Pimenta, K. Makinwa

引用次数: 25