2019 IEEE International Solid- State Circuits Conference - (ISSCC)最新文献

{"title":"8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation","authors":"C. Schaef, Nachiket V. Desai, H. Krishnamurthy, Sheldon Weng, H. Do, William J. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De","doi":"10.1109/ISSCC.2019.8662294","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662294","url":null,"abstract":"Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $lt/pgtlt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114516258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"7.1 An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC","authors":"Jinook Song, Yun-Jin Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joonho Song, Jae-Gon Lee, Inyup Kang","doi":"10.1109/ISSCC.2019.8662476","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662476","url":null,"abstract":"Deep learning has been widely applied for image and speech recognition. Response time, connectivity, privacy and security drive applications towards mobile platforms rather than cloud. For mobile systems-on-a-chip (SoCs), energy-efficient neural processing units (NPU) have been studied for performing the convolutional layers (CLs) and fully-connected layers (FCLs) [2–5] in deep neural networks. Moreover, considering that neural networks are getting deeper, the NPU needs to integrate 1K or even more multiply/accumulate (MAC) units. For energy efficiency, compression of neural networks has been studied by pruning neural connections and quantizing weights and features with 8b or even lower fixed-point precision without accuracy loss [1]. A hardware accelerator exploited network sparsity for high utilization of MAC units [3]. However, since it is challenging to predict where pruning is possible, the accelerator needed complex circuitry for selecting an array of features corresponding to an array of non-zero weights. For reducing the power of MAC operations, bit-serial multipliers have been applied [5]. Generally, extremely low- or variable-bit-precision neural networks need to be carefully trained.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129510262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ISSCC 2019 Session 23 Overview: DRAM","authors":"","doi":"10.1109/isscc.2019.8662288","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662288","url":null,"abstract":"","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124321213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"15.2 A 90ns/V Fast-Transition Symbol-Power-Tracking Buck Converter for 5G mm-Wave Phased-Array Transceiver","authors":"Ji-Seon Paek, Takahiro Nomiyama, Jae-Yeol Han, Ik-Hwan Kim, Yumi Lee, Dongsu Kim, Euiyoung Park, Sung-Jun Lee, Jongwoo Lee, T. Cho, Inyup Kang","doi":"10.1109/ISSCC.2019.8662420","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662420","url":null,"abstract":"The 5G-New-Radio (NR) standard in millimeter wave (mm-wave) bands requires a low-cost antenna module consisting of a phased-array transceiver with beamforming [1], an antenna array, and a power management IC (PMIC). Since a typical on-chip mm-wave CMOS power-amplifier (PA) arrays have poor power efficiency due to the lossy substrate and the low maximum available-gain frequency of CMOS processes, they cause serious thermal issues due to the high power density and reduce battery life in a mobile handset. Recently, supply-modulation (SM) techniques, such as an envelope tracking (ET) and an average-power tracking (APT) instead of a direct battery-connected supply, have been introduced to enhance PA efficiency [2]. However, these techniques have few challenges, such as limited ET tracking bandwidth and APT transition time, to support new requirements of the 5G NR standard. In order to manage the power effectively of a phased-array module, a special SM technique named symbol-power tracking (SPT) is proposed for the power management in this work. The SPT controls the supply voltage of mm-wave PA arrays every few micro-second (symbol to symbol), which is much faster than that of APT, which adjusts the output voltage every one millisecond (sub-frame to sub-frame).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127875331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"4.1 A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency","authors":"Aoyang Zhang, M. Chen","doi":"10.1109/ISSCC.2019.8662511","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662511","url":null,"abstract":"Modern wireless communication systems often utilize spectrum-efficient modulation schemes for higher data throughput, given the finite bandwidth. This type of modulation schemes, such as Orthogonal Frequency Division Multiplexing (OFDM), results in a high peak-to-average power ratio (PAPR) for the transmitted signal. Therefore, power amplifier efficiency in the power back-off (PBO) region has become an important design target. Meanwhile, obtaining high output power and high average efficiency still remains a key design challenge when developing an integrated CMOS PA. Recently, a subharmonic switching (SHS) digital PA architecture was reported in [1]. It toggles the PA cell at the subharmonic component of the carrier frequency (Fc) to achieve power back-off. The slower toggling rate reduces dynamic and conduction loss in the switching PA, resulting in better PBO efficiency. However, the SHS PA requires additional notch filtering of the subharmonic components in the matching network. Therefore, we propose a phase-interleaved architecture that combines three SHS PAs to increase output power (Watt-level) and inherently cancel the subharmonic components in the PBO mode, thereby alleviating the burden of the matching network. Moreover, multiple subharmonic components are utilized to create a greater number of efficiency peaks in the PBO region. This is referred to as a multi-SHS scheme. Lastly, a hybrid Class-G operation, in combination with the multi-SHS scheme, is used to further enhance average efficiency.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127883883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS","authors":"A. Ramkaj, J. P. Ramos, Yifan Lyu, M. Strackx, Marcel J. M. Pelgrom, M. Steyaert, M. Verhelst, F. Tavernier","doi":"10.1109/ISSCC.2019.8662490","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662490","url":null,"abstract":"Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1–4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1–5].","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"18.6 A 32MHz Crystal Oscillator with Fast Start-up Using Synchronized Signal Injection","authors":"B. Verhoef, J. Prummel, W. Kruiskamp, R. Post","doi":"10.1109/ISSCC.2019.8662338","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662338","url":null,"abstract":"Low-power sensor nodes (e.g., Bluetooth Low Energy, BLE) use low duty-cycle transceivers to obtain an overall low power consumption. The system typically spends most of the time in a low-power sleep state and only briefly wakes up to transmit and receive data. Due to the high Q (>100k) of the crystal resonator the start-up time of a typical crystal oscillator is relatively long ($approx 0.5$ to 5ms) which causes a substantial amount of energy to be consumed by the crystal oscillator in a transmit/receive event. As the system usually is in an active state when the crystal oscillator ramps up (multiple sub-systems are powered up) not only should the start-up energy of the crystal oscillator be optimized, but also the startup time. As the crystal resonator is one of the most costly components in IoT sensor nodes, a wide range of crystal resonators should be supported by the circuit. This work proposes a synchronized signal injection (SSI) start-up mechanism that can drive the crystal up to any amplitude in a minimum amount of time, does not require a high-precision RC oscillator, is insensitive to PTV and is effective for a wide range of crystals: the technique does not require the shunt capacitance or the load capacitance to be small. A programmable capacitor-bank is included to support a range of crystals (load-capacitance) and allow for the customer to calibrate the frequency but is not required for the SSI technique.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"5.6 A 400×400-Pixel 6μm-Pitch Vertical Avalanche Photodiodes CMOS Image Sensor Based on 150ps-Fast Capacitive Relaxation Quenching in Geiger Mode for Synthesis of Arbitrary Gain Images","authors":"Y. Hirose, S. Koyama, T. Okino, Akito Inoue, S. Saito, Yugo Nose, M. Ishii, S. Yamahira, S. Kasuga, M. Mori, T. Kabe, K. Nakanishi, M. Usuda, A. Odagawa, Tsuyoshi Tanaka","doi":"10.1109/ISSCC.2019.8662405","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662405","url":null,"abstract":"The intensive development of Single-photon avalanche photodiode (SPAD) based CMOS image sensors (CIS) continues, with rapid progress [1–6]. Yet, due to unestablished quenching operation [5,6], realization of SPADs onto a CIS alongside conventional pixel circuitry has been a fundamental challenge.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121602879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET","authors":"A. Cevrero, Ilter Özkaya, P. Francese, M. Brändli, C. Menolfi, T. Morf, M. Kossel, L. Kull, D. Luu, M. Dazzi, T. Toifl","doi":"10.1109/ISSCC.2019.8662495","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662495","url":null,"abstract":"The growing demand for higher data rates in wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses $(gt20$ dB) [1], but their power consumption $(gt500$ mW/lane excluding DSP) is prohibitive for applications requiring large port counts in short-reach chip-to-chip and chip-to-module links (such as OIF-CEI-112G-VSR/XSR/USR). This work demonstrates a dual PAM-4/NRZ RX implemented in 14nm FinFET and measured up to 100Gb/s in PAM-4 mode achieving pre-FEC BER $lt 10^{-12}$ across a 19.2dB-loss channel with low power. To achieve low BER with $gt16$ dB loss channel the RX uses a CTLE combined with a 1-tap speculative DFE. To minimize power consumption, the number of slicing levels to resolve the 1-tap PAM-4 DFE speculation is reduced from 12 to 8 by shaping the channel to a1 +0.5D response (h 0 +0.5 $ast$ h0) with CTLE and TXFFE. With a1 +0.5D channel, 4 out of 12 speculative decisions are overlapped. Moreover, comparators used for DFE speculation can be shared for phase detection in a baud-rate CDR scheme, extending the concept proposed in [2] to PAM-4. In NRZ mode, the RX features a fully speculative 3-tap DFE to equalize high loss channels $(gt35$ dB) at 56Gb/s. The RX incorporates the following key advances: (1) a trans-admittance trans-impedance (TAS-TIS) CTLE circuit resulting in a low-power and compact analog-front-end (AFE), (2) a 1-tap PAM-4 speculative DFE based on a1 +0.5D response, and (3) a CMOS quadrature-DLL (QDLL) generating quadrature clock phases resulting in a low jitter/power clock path.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133010491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"16.5 A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax","authors":"Fei Song, Yu Zhao, Bart Wu, L. Tang, Leon Lin, B. Razavi","doi":"10.1109/ISSCC.2019.8662488","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662488","url":null,"abstract":"The next-generation 802.11ax WLAN standard improves the throughput by supporting 1024-QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the transmitter (Tx) and the receiver (Rx) synthesizers. Recent work has achieved rms jitter below 200fs [1]–[4] with the latest rms jitter reported at 75fs [5]. The work in [5] faces a number of challenges if applied to 802.11ax: (1) with a VCO frequency of 5.7 to 7.3GHz, the circuit is prone to pulling by the PA, especially because it incorporates a single spiral inductor (rather than an 8shaped inductor); (2) it does not provide quadrature outputs, and (3) it relies on a 10b digital-to-time converter (DTC) without calibration of its nonlinearity, which folds high-frequency $Delta Sigma-text { modulator } (Delta Sigma M)$ noise unless extremely tight matching is guaranteed. Similarly, the design in [2] is prone to pulling as well.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132447340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}