{"title":"Enterprise Job Scheduling for Clustered Environments","authors":"Stratos Paulakis, V. Tsetsos, S. Hadjiefthymiades","doi":"10.1109/ISORC.2007.34","DOIUrl":"https://doi.org/10.1109/ISORC.2007.34","url":null,"abstract":"The concept of scheduling is relevant to many computer-engineering areas, such as operating systems, computer networks, enterprise platforms and applications. Scheduling at the application level (a.k.a. job scheduling) is a common process in the enterprise domain, but very few IT solutions cover all the required features. Such features include scalability, fault-tolerance and load balancing. In this paper, we present the design and implementation of a modular job scheduling system, developed to work in a distributed clustered environment, which satisfies the aforementioned requirements. Its architecture and implementation is based on the Java 2 Enterprise Edition (J2EE) framework so that it inherently guarantees portability over different platforms through the use of open interfaces. A preliminary performance evaluation of the system provides indications on its behavior under various levels of workload","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124251843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated Formal Verification and Testing of C Programs for Embedded Systems","authors":"Susanne Kandl, R. Kirner, P. Puschner","doi":"10.1109/ISORC.2007.22","DOIUrl":"https://doi.org/10.1109/ISORC.2007.22","url":null,"abstract":"In this paper, we introduce an approach for automated verification and testing of ANSI C programs for embedded systems. We automatically extract an automaton model from the C code of the SUT (system under test). This automaton model is on the one hand used for formal verification of the requirements defined in the system specification, on the other hand, we can derive test cases from this model, for both methods we use a model checker. We describe our techniques for test case generation, based on producing counterexamples with a model checker by formulating trap properties. The resulting test cases can then be applied to the SUT on different test levels. An important issue for model checking C-source code, is the correct modeling of the semantics of a C program for an embedded system. We focus on challenges and possible restrictions that appear, when model checking is used for the verification of C-source code. We specifically show how to deal with arithmetic expressions in the model checker NuSMV and how to preserve the numerical results in case of modeling the platform-specific semantics of C","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125280155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Engineering Self-Coordinating Real-Time Systems","authors":"F. Rammig","doi":"10.1109/ISORC.2007.33","DOIUrl":"https://doi.org/10.1109/ISORC.2007.33","url":null,"abstract":"In this paper we present our vision of establishing self-coordination as the dominant paradigm of operation of future embedded computing environments. This vision is looked at from three different points of view. First of all techniques to model self-coordinating distributed systems in an adequate manner and algorithmic techniques for such systems are discussed. Then the principle of self-coordination is applied to build proper system structures. In a next step such objects are enabled to communicate. Again the potential of self-coordination, now applied to the communication infrastructures is studied. Some proper examples are used to illustrate the approaches and the potentials of self-coordination","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"3 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130278112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Efficient Algorithm for Online Soft Real-Time Task Placement on Reconfigurable Hardware Devices","authors":"Jin Cui, Z. Gu, Weichen Liu, Qingxu Deng","doi":"10.1109/ISORC.2007.18","DOIUrl":"https://doi.org/10.1109/ISORC.2007.18","url":null,"abstract":"Reconfigurable devices such as field programmable gate arrays (FPGAs) are very popular in today's embedded systems (design due to their low-cost, high-performance and flexibility. Partially runtime-reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the real-time research community compared to software task scheduling on CPUs. In this paper, we present an efficient online task placement algorithm for minimizing fragmentation on PRTR FPGAs. First, we present a novel 2D area fragmentation metric that takes into account probability distribution of sizes of future task arrivals; second, we take into the time axis to obtain a 3D fragmentation metric. Simulation experiments indicate that our techniques result in low ratio of task rejection and high FPGA utilization compared to existing techniques","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130868710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache","authors":"R. Kirner, P. Puschner","doi":"10.1109/ISORC.2007.56","DOIUrl":"https://doi.org/10.1109/ISORC.2007.56","url":null,"abstract":"Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121152869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Shankaran, D. Schmidt, X. Koutsoukos, Yingming Chen, Chenyang Lu
{"title":"Design and Performance Evaluation of Configurable Component Middleware for End-to-End Adaptation of Distributed Real-Time Embedded Systems","authors":"N. Shankaran, D. Schmidt, X. Koutsoukos, Yingming Chen, Chenyang Lu","doi":"10.1109/ISORC.2007.27","DOIUrl":"https://doi.org/10.1109/ISORC.2007.27","url":null,"abstract":"Standards-based quality of service (QoS)-enabled component middleware is increasingly being used as a platform for developing distributed real-time embedded (DRE) systems that execute in open environments where operational conditions, input workload, and resource availability cannot be characterized accurately a priori. Although QoS-enabled component middleware offers many desirable features, until recently it lacked the ability to efficiently allocate resources and configure platform-specific QoS settings based on utilization of system resources and application QoS. Moreover, it has also lacked the ability to monitor and enforce application QoS requirements. This paper presents two contributions to research on adaptive resource management for component-based DRE systems. First, we describe the structure and functionality of the resource allocation and control engine (RACE), which is an open-source adaptive resource management framework built atop standards-based QoS-enabled component middleware. Second, we demonstrate the effectiveness of RACE in the context of a representative DRE system: NASA's magneto spheric multi-scale mission system","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128929898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takuya Azumi, Masahiro Yamamoto, Y. Kominami, N. Takagi, Hiroshi Oyama, H. Takada
{"title":"A New Specification of Software Components for Embedded Systems","authors":"Takuya Azumi, Masahiro Yamamoto, Y. Kominami, N. Takagi, Hiroshi Oyama, H. Takada","doi":"10.1109/ISORC.2007.7","DOIUrl":"https://doi.org/10.1109/ISORC.2007.7","url":null,"abstract":"In the last decade, the size and complexity of the software in embedded systems have increased. The present study attempts to decrease the complexity and difficulty of software development in embedded systems. We herein introduce a new component system that is suitable for embedded systems. It is possible to estimate the memory consumption of an entire application since the proposed system adopts a static configuration. In addition, this system takes into account to be used in several domains of embedded systems because several particle sizes of component are supported. Moreover, the concept of the component for a distributed application is presented","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116969430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Timed-Automata Semantics and Analysis of UML/SPT Models with Concurrency","authors":"Abdelouahed Gherbi, F. Khendek","doi":"10.1109/ISORC.2007.57","DOIUrl":"https://doi.org/10.1109/ISORC.2007.57","url":null,"abstract":"UML can be effectively used for the design and analysis of real-time systems. UML profiles for real-time, like the current OMG's standard UML/SPT, enable the modeling of quantitative requirements such as time constraints as well as behavioral features such as concurrency. Because of the multitude of diagrams and their complexity, UML/SPT models face the challenging issue of consistency. In this paper, we look into the behavioral consistency and particularly into concurrency-related properties of UML/SPT models. In order to do so, we formally define the UML/SPT concurrency domain model in terms of timed automata. As a straightforward application of this semantics, UML/SPT concurrent models can be validated using well-established model checking techniques and tools","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Iterative Refinement Framework for Tighter Worst-Case Execution Time Calculation","authors":"Hojung Bang, T. Kim, S. Cha","doi":"10.1109/ISORC.2007.19","DOIUrl":"https://doi.org/10.1109/ISORC.2007.19","url":null,"abstract":"This paper presents an iterative refinement framework for static WCET analysis based on implicit path enumeration technique (IPET). We check the feasibility of IPET solutions, convert infeasible solutions to path constraints to exclude them from the analysis, and recalculate estimates whenever new path constraints are added. This process is repeated until no more constraints are extracted or a predefined time limit is reached. Since infeasible path detection itself is an undecidable problem, we propose an approximate method that checks feasibility efficiently while preserving safeness of the results. Generated path constraints are free of disjunctions; thus, amenable to integer linear program (ILP) solvers, which are used in IPET. We demonstrated the effectiveness and efficiency by conducting an experiment, where a module of flight control software of a commercial satellite developed in Korea was used","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115828040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Component-Based Methodology to Design Arbitrary Failure Detectors for Distributed Protocols","authors":"R. Baldoni, J. Hélary, S. Piergiovanni","doi":"10.1109/ISORC.2007.6","DOIUrl":"https://doi.org/10.1109/ISORC.2007.6","url":null,"abstract":"Nowadays, there are many protocols able to cope with process crashes, but, unfortunately, a process crash represents only a particular faulty behavior. Handling tougher failures (e.g. sending omission failures, receive omission failures, arbitrary failures) is a real practical challenge due to malicious attacks or unexpected software errors. This paper proposes a component-based methodology allowing to take a protocol A resilient to crash failures and to add software components, namely liveness and safety failure detectors, in order to adapt the protocol A to be resilient to more general failures than crashes, without changing the code of A. Then, the feasibility of this approach is shown, by providing an implementation of liveness failure detectors and of safety failure detectors for a protocol solving the problem of global data computation","PeriodicalId":265471,"journal":{"name":"10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}