Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion最新文献_第2页

Prediction based convolution neural network acceleration: work-in-progress 基于卷积神经网络加速预测的研究进展

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125523

Y. Yao, Zhonghai Lu

引用次数: 0

A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress 一个“高弹性”模式，以尽量减少ARM cortex-R CPU管道中的软错误漏洞:正在进行中

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125509

X. Iturbe, Balaji Venu, John Penton, Emre Ozer

引用次数: 1

Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress 通过恢复感知内存管理，使用STT-MRAM启用可靠的主存:正在进行的工作

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125517

Armin Haj Aboutalebi, Lide Duan

{"title":"Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress","authors":"Armin Haj Aboutalebi, Lide Duan","doi":"10.1145/3125501.3125517","DOIUrl":"https://doi.org/10.1145/3125501.3125517","url":null,"abstract":"As an important non-volatile memory technology, STT-MRAM is widely considered as a universal memory solution in current processors. Employing STT-MRAM as the main memory offers a wide variety of benefits, but also results in unique design challenges. In particular, read disturbance characterizes accidental data corruption in STT-MRAM after it is read, leading to a need of restoring data back to memory after each read operation. These extra restores significantly degrade system performance and energy efficiency, greatly changing the timing scenarios that conventional designs were optimized for. As a result, directly adopting conventional, restore-agnostic memory management techniques may lead to sub-optimal designs for STT-MRAM. In this work, we propose Restore-Aware Policy Selection (RAPS), a dynamic and hybrid row buffer management scheme that factors in the inevitable data restores in STT-MRAM-based main memory. RAPS monitors the row buffer hit rate at run time, dynamically switching between the open- and close-page policies. By factoring in restores, RAPS accurately captures the optimal design points, achieving optimal policy selections at run time. Our experimental results show that RAPS significantly improves system performance and energy efficiency compared to the conventional policies.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115213782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress 使用PCIe虚拟通道改进NVMe SSD I/O确定性:正在进行中

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125520

Seonbong Kim, Joon-Sung Yang

引用次数: 0

Multi-grained performance estimation for MPSoC compilers: work-in-progress MPSoC编译器的多粒度性能估计:正在进行的工作

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125521

M. Aguilar, Abhishek Aggarwal, Awaid Shaheen, R. Leupers, G. Ascheid, J. Castrillón, L. Fitzpatrick

引用次数: 3

A high-performance FPGA accelerator for sparse neural networks: work-in-progress 用于稀疏神经网络的高性能FPGA加速器:正在开发中

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125510

Yuntao Lu, Lei Gong, Chongchong Xu, Fan Sun, Yiwei Zhang, Chao Wang, Xuehai Zhou

引用次数: 6

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress) SSS:采用静动态混合方法的自感知片上系统(在研)

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125527

Gaoming Du, Shibi Ma, Zhenmin Li, Zhonghai Lu, Yiming Ouyang, M. Gao

{"title":"SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress)","authors":"Gaoming Du, Shibi Ma, Zhenmin Li, Zhonghai Lu, Yiming Ouyang, M. Gao","doi":"10.1145/3125501.3125527","DOIUrl":"https://doi.org/10.1145/3125501.3125527","url":null,"abstract":"Network on chip has become the de facto communication standard for multi-core or many-core system on chip, due to its scalability and flexibility. However, temperature is an important factor in NoC design, which affects the overall performance of SoC---decreasing circuit frequency, increasing energy consumption, and even shortening chip lifetime. In this paper, we propose SSS, a self-aware SoC using a static-dynamic hybrid method, which combines dynamic mapping and static mapping to reduce the hot-spots temperature for NoC based SoCs. First, we propose monitoring the thermal distribution for self-state sensoring. Then, in static mapping stage, we calculate the optimal mapping solutions under different temperature modes using discrete firefly algorithm to help self-decision making. Finally, in dynamic mapping stage, we achieve dynamic mapping through configuring NoC and SoC sentient unit for self-optimizing. Experimental results show SSS can reduce the peak temperature by up to 30.64%. FPGA prototype shows the effectiveness and smartness of SSS in reducing hot-spots temperature.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126179521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Efficient pulsed-latch implementation for multiport register files: work-in-progress 多端口寄存器文件的高效脉冲锁存器实现:正在进行的工作

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125515

W. Elsharkasy, Hasan Erdem Yantır, A. Djahromi, A. Eltawil, F. Kurdahi

引用次数: 2

Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125516

Hao Yan, Ethan C. Ahn, Lide Duan

{"title":"Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress","authors":"Hao Yan, Ethan C. Ahn, Lide Duan","doi":"10.1145/3125501.3125516","DOIUrl":"https://doi.org/10.1145/3125501.3125516","url":null,"abstract":"Apart from employing a co-processor (e.g., GPU) for neural network (NN) computation, utilizing the unique characteristics of nonvolatile memories (NVM), including RRAM, phase change memory (PCM), and STT-MRAM, to accelerate NN algorithms has been extensively studied. In such approaches, input data and synaptic weights are represented using word line voltages and cell resistance, with the resulting bit line current indicating the calculation result. However, the limited number of resistance levels in a NVM cell largely reduces the algorithm data precision, thus significantly lowering the model inference accuracy. Motivated by the observation that the conventional, uniformly generated data quantization points are not equally important to the model, we propose a nonuniform data quantization scheme to better represent the model in NVM cells and minimize the inference accuracy loss. Our experimental results show that the proposed scheme can achieve highly accurate deep learning model inference using as low as only 4 bits for synaptic weight representation. This effectively enables a NVM with few cell resistance levels (e.g., STT-MRAM) to perform NN calculation, and also results in additional benefits in performance, energy, and memory storage.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123691857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress) REDEFINE®™:用于实时应用的wcet友好硬件加速器案例(正在开发中)

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI: 10.1145/3125501.3125526

K. Madhu, Tarun Singla, S. Nandy, R. Narayan, Francois Neumann, P. Baufreton

引用次数: 0