一个“高弹性”模式，以尽量减少ARM cortex-R CPU管道中的软错误漏洞:正在进行中

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion Pub Date : 2017-10-15 DOI:10.1145/3125501.3125509

X. Iturbe, Balaji Venu, John Penton, Emre Ozer

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引用次数: 1

摘要

本文提出了一种“高弹性”执行模式，以提高CPU管道在执行关键软件例程时对软错误的鲁棒性。所提出的执行模式在ARM Cortex-R5 CPU中减少了大约11%的错误率，并且只需要对其微架构进行一些微小的修改。这些修改不影响原有CPU的特征面积、功耗和性能特征。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress

This paper proposes a "high resilience" execution mode to increase the robustness of CPU pipelines to soft errors when executing critical software routines. The proposed execution mode reduces the error rate by approximately 11% in an ARM Cortex-R5 CPU, and requires only a few minor modifications to be made in its microarchitecture. These modifications do not impact the characteristic area, power consumption and performance features of the original CPU.

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Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion

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