2007 International Conference on Signal Processing, Communications and Networking最新文献_第5页

Adaptive Gray Level Difference to Speed Up Fractal Image Compression 自适应灰度差加速分形图像压缩

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350741

V. R. Prasad, Vaddella, R. Babu, Inampudi

{"title":"Adaptive Gray Level Difference to Speed Up Fractal Image Compression","authors":"V. R. Prasad, Vaddella, R. Babu, Inampudi","doi":"10.1109/ICSCN.2007.350741","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350741","url":null,"abstract":"Fractal image compression is a lossy compression technique that has been developed in the early 1990s. It makes use of the local self similarity property existing in an image and finds a contractive mapping affine transformation (fractal transform) T, such that the fixed point of T is close to the given image in a suitable metric. It has generated much interest due to its promise of high compression ratios with good decompression quality. The other advantage is its multiresolution property, i.e. an image can be decoded at higher or lower resolutions than the original without much degradation in quality. However, the encoding time is computationally intensive. In this paper, a new method to reduce the encoding time based on computing the gray level difference of domain and range blocks, is presented. A comparison for best match is performed between the domain and range blocks only if the range block gray level difference is less than the domain block gray level difference. This reduces the number of comparisons, and thereby the encoding time considerably, while obtaining good fidelity and compression ratio for the decoded image. Experimental results on standard gray scale images (512times512, 8 bit) show that the proposed method yields superior performance over conventional fractal encoding","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115902107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An Efficient Location Tracking Algorithm for MANET using Directional Antennas 一种有效的定向天线MANET定位跟踪算法

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350718

K. Kathiravan, S. Thamarai Selvi

{"title":"An Efficient Location Tracking Algorithm for MANET using Directional Antennas","authors":"K. Kathiravan, S. Thamarai Selvi","doi":"10.1109/ICSCN.2007.350718","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350718","url":null,"abstract":"In order to implement effective directional medium access control (DMAC) protocol and routing protocol in mobile ad hoc networks (MANET), each node in the network should know how to set its transmission direction to transmit a packet to its neighbors. So, it becomes imperative to have a mechanism at each node to track the locations of its neighbors under mobility condition. In this paper, an efficient location tracking algorithm for MANET using directional antennas with fixed beams is proposed to maintain communication between two communicating nodes. The proposed algorithm works in conjunction with the DMAC protocol. The transmitting node will monitor its received power level from the neighboring node's acknowledgement packet transmission. If the received power falls below the threshold, the node indicates the need to switch the antenna element to its data link layer. The DMAC protocol in the data link layer will switch the transmitting antenna either in the clockwise or anticlockwise direction of the active antenna and check for the induced power. Whichever antenna has picked up the signal with sufficient signal strength, handoff takes place from the active antenna to the new antenna. We have shown through simulations, that the mechanism is suitable in highly mobile scenarios. The throughput falls regularly as nodes lose their connection without location tracking. But, the throughput remains a constant or there is a slight dip at the switching time interval when the location tracking is implemented with DMAC","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116014537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A New Fast Convergence Adaptive Algorithm 一种新的快速收敛自适应算法

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350719

P. Palanisamy, N. Kalyanasundaram

引用次数: 2

A Service Time Error Based Scheduling Algorithm for a Computational Grid 基于服务时间误差的计算网格调度算法

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350663

D. Lopez, Rasika Chakravarthy

引用次数: 1

FPGA Implementation of Parallel Pipelined Multiplier Less FFT Architecture Based System-On-Chip Design Targetting Multimedia Applications 面向多媒体应用的片上系统设计并行流水线无乘法器FFT架构的FPGA实现

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350677

B. Sreejaa, T. Jayanthy, E. Logashanmugam

引用次数: 0

Modified Conservative Staircase Scheme for Video Services 改进的视频业务保守楼梯方案

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350681

H. Om, S. Chand

引用次数: 0

Hash Mapping Strategy for Improving Retrieval Effectiveness in Semantic Cache System 提高语义缓存系统检索效率的哈希映射策略

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350737

M. Sumalatha, V. Vaidehi, A. Kannan, M. Rajasekar, M. Karthigaiselvan

{"title":"Hash Mapping Strategy for Improving Retrieval Effectiveness in Semantic Cache System","authors":"M. Sumalatha, V. Vaidehi, A. Kannan, M. Rajasekar, M. Karthigaiselvan","doi":"10.1109/ICSCN.2007.350737","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350737","url":null,"abstract":"The emergence of Web applications has encouraged us to have much recent research on data caching. In our proposed work we have given a new strategy, dynamic hash mapping technique which gives fast information retrieval semantically with the cache. This increases the speed up in the information retrieval for semantic caching which is a method of data caching where it is rule based. The semantic caching technology can help to improve the efficiency of XML query processing in the Web environment. Unlike from the traditional tuple or page-based caching systems, semantic caching systems exploit the idea of reusing cached query results to answer new queries based on the query containment and rewriting techniques. The primary contribution of this article is to revisit the performance of semantic caching by this new mapping technique, which increases the efficiency in information retrieval in the semantic caching system. Our proposed method gives enhanced performance by reduced network traffic and searches the exact information from a large database, which is crucial, in a range of applications, especially in network-constrained environments","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126070856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Performance Evaluation of One Dimensional Systolic Array for FFT Processor FFT处理器一维收缩阵列性能评价

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350724

A. Nandi, S. Patil

引用次数: 3

On-Board Verification of FPGA Based Digital Systems using NIOS Processor (A Methodology Without Hook-Ups and I/O Cards) 基于FPGA的NIOS处理器数字系统板上验证(无连接和I/O卡的方法)

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350678

G. Lakshminarayanan, T. Prabakar

{"title":"On-Board Verification of FPGA Based Digital Systems using NIOS Processor (A Methodology Without Hook-Ups and I/O Cards)","authors":"G. Lakshminarayanan, T. Prabakar","doi":"10.1109/ICSCN.2007.350678","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350678","url":null,"abstract":"A novel methodology for testing all digital systems fused onto the FPGA has been developed in this paper. This methodology does not require any hook-up and input/output (I/O) interfacing card. This methodology uses the NIOS processor core to configure system onto the FPGA. HDL code of the digital system along with NIOS core is downloaded onto the FPGA. The NIOS processor can be programmed, to supply all possible combinations of test vectors to the digital system and read back the results generated by the digital system. The results are compared with the expected results on the NIOS processor and the errors displayed. After studying the error, the HDL code is tuned and the process is repeated till getting zero error. Once the process is completed, either the HDL code of the tested digital system or macro of the tested digital system can be a physically proven digital system. The advantage of this methodology is that, high throughput of the digital systems can be verified; by considering that NIOS II frequency is adequate to supply the test vectors. By the way, the time required to verify the digital system with all possible combinations of test vectors is greatly reduced","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131619784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Artifacts Removal in EEG Signal using Adaptive Neuro Fuzzy Inference System 基于自适应神经模糊推理系统的脑电信号伪影去除

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI: 10.1109/ICSCN.2007.350676

C. Kezi Selva Vijilal, P. Kanagasabapathy, Stanly Johnson Jeyaraj, V. Ewards

引用次数: 20