{"title":"High-performance NTT architecture for large integer multiplication","authors":"Jheng-Hao Ye, Ming-Der Shieh","doi":"10.1109/VLSI-DAT.2018.8373254","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373254","url":null,"abstract":"This paper presents an efficient architecture of number Theoretical transform (NTT), targeting at fulfilling large integer multiplication for fully homomorphic encryption applications. A systematic memory management scheme is proposed for the pipelined shared-memory NTT architecture implemented with mixed-radix multi-path delay commutators (MDCs). The presented data relocation scheme along with the MDC can be applied to merge multiple banks with single-port memory for further reducing the area requirement. Experimental results show that a 1,179,648-bit multiplier implemented by the proposed solution, including seamless data transfer among the building blocks, can lead to more than 39.8% area reduction with even a lower computational time as compared with the related works.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124985553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A digital peak current delay compensation for primary-side regulation flyback adapter","authors":"Chun-Ping Niou, Chien-Hung Tsai, T. Chen","doi":"10.1109/VLSI-DAT.2018.8373260","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373260","url":null,"abstract":"A digital control primary-side regulation (PSR) flyback adapter with peak current delay compensation technique is proposed. In USB type adapters, over-current protection (OCP) or constant current (CC) control is used to protect the system. However, there is a primary-side peak current detection error caused by the propagation delay in control circuits, which makes the OCP and CC control incorrect. This paper proposes a digital method named as two-cycle-averaged compensation to solve current variation caused by the propagation delay. This work can reduce the cost of digital hardware, and without losing the compensation effect. The output current accuracy measurement result of this work is smaller than 2.8%.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132579043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, M. Yamaoka, M. Yanagisawa, N. Togawa
{"title":"An Ising model mapping to solve rectangle packing problem","authors":"Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, M. Yamaoka, M. Yanagisawa, N. Togawa","doi":"10.1109/VLSI-DAT.2018.8373233","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373233","url":null,"abstract":"Floorplanning of modules has been a significant role in VLSI design automation and it can be formulated as the \"Rectangle Packing Problem.\" Ising model-based computers (or annealing machines) are the type of a non-von Neumann computer and recently expected to solve combinatorial optimization problems efficiently. In this paper, we propose a mapping of \"Rectangle Packing Problem\" for solving it by the annealing machines. In our proposed mapping, a sequence-pair is represented on an Ising model. Our proposed approach maps a \"Rectangle Packing Problem\" with N rectangles onto a 3N3-spin logical Ising model. Experimental results demonstrate that through the proposed approach we can solve the problem with 18 rectangles at the maximum on a fully-connected annealing machine and the problem with three rectangles at the maximum on 20k-spin CMOS annealing machine.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134204476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-throughput Von Neumann post-processing for random number generator","authors":"Ruilin Zhang, Sijia Chen, Chao Wan, H. Shinohara","doi":"10.1109/VLSI-DAT.2018.8373253","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373253","url":null,"abstract":"This paper presents the improvement and implementation of N bits Von Neumann (VN_N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN_N and circuit level implementation of 4 bits VN_4 are shown. VN_4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN_4+waiting and VN_8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN_2) with 25.0%, respectively.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kun-Ying Yeh, Ting-Hao Lin, Yi-Yen Hsieh, Chia-Ming Chang, Y. Yang, Shey-Shi Lu
{"title":"A cuffless wearable system for real-time cutaneous pressure monitoring with cloud computing assistance","authors":"Kun-Ying Yeh, Ting-Hao Lin, Yi-Yen Hsieh, Chia-Ming Chang, Y. Yang, Shey-Shi Lu","doi":"10.1109/VLSI-DAT.2018.8373251","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373251","url":null,"abstract":"The pulse pressure variation associated with arterial blood flow is a valuable indicator for early diagnosis of cardiovascular diseases, which could lead to lots of health problems if left untreated. To detect the subtle wrist artery pressure, a cuffless wearable integrated system using a tunneling piezoresistive sensor, which achieves ultrahigh sensitivity, is presented in this paper. After the readout circuit amplifies and converts the pulse pressure-induced signal, a wireless communication module transmits the data to intellectual devices and eventually to the cloud storage. Real-time and sustainable pulse pressure monitoring is demonstrated from sensor detection to cloud computing. Through the digital signal processing, long-term pulse pressure monitoring improves the accuracy of cuffless applications, and measured data can accomplish cardiovascular event fast screening after being processed by Hilbert Huang transform (HHT), pulse rate variability (PRV), and multi-scale entropy (MSE) analysis.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121805474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Noguchi, Kosuke Furuichi, H. Uemura, Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Hiroaki Katsurai, S. Nakano, H. Nosaka
{"title":"A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS","authors":"R. Noguchi, Kosuke Furuichi, H. Uemura, Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Hiroaki Katsurai, S. Nakano, H. Nosaka","doi":"10.1109/VLSI-DAT.2018.8373224","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373224","url":null,"abstract":"A 25-Gb/s low-power Clock and Data Recovery (CDR) with Clocked CMOS (C2MOS) D-Flip-Flop (D-FF) for low power operation is presented. In a CDR circuit, D-FF is one of the dominant factor on the power consumption. In this work, we design the low-power CDR with 25-GHz clock by using a C2MOS D-FF. C2MOS D-FF reduces the power by 84 % compared with a conventional current mode logic (CML) D-FF. To validate the proposed design, we fabricated 25-Gb/s CDR in a 65-nm CMOS process. The area for the core circuits is 0.047 mm2, and the power consumption without output buffers is 13 mW, which is 13 % of that for the conventional 65-nm CDR with 25-GHz clock.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fast ECG diagnosis by using spectral artificial neural network (SANN) approach","authors":"K. Chen, Po-Chen Chien","doi":"10.1109/VLSI-DAT.2018.8373248","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373248","url":null,"abstract":"Electrocardiogram (ECG) diagnosis is a widely-used clinical approach because it has been proven as an efficient way to monitor and diagnose cardiac diseases. However, because of a large amount of the raw ECG signal data, it is time-consuming to analyze the ECG signal. Moreover, ECG signal analysis is a nonlinear problem, which worsens the difficulty to diagnose the ECG signal. Therefore, many Neural Network (NN)-based ECG analysis approaches were proposed to perform ECG diagnosis in time domain in recent years, which can improve the ability of ECG analysis. By decomposing the ECG signal, the P, Q, R, S, and T waves can be acquired for the further analysis based on the information of the features of these waves such as the amplitude and waves interval. However, because of the complex pre-process for the signal purification and feature extraction, this kind of time-domain ECG signal process still suffers from the long computation time. To solve the problem, we propose a Spectral Artificial Neural Network (SANN) approach for the fast ECG diagnosis in this paper. Compared with the conventional time-domain-based approaches, the SANN analyzes the ECG signal in frequency domain. Because most of the noises in the raw ECG signal are high-frequency signals, the proposed SANN focuses to analyze the low-frequency signals in ECG spectrum. By this way, the proposed SANN not only reduces the pre-processing time but the diagnosis time. To obtain the proper window size for the precise ECG diagnosis, we further propose a heuristic window size adjustment in this paper, which helps to extract the suitable features. The experimental results show that the proposed SANN approach can reduce the ECG diagnosis time by 80% compared with the conventional ECG analysis with only 5% average diagnosis accuracy loss of the cardiac diseases.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125815329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Deep fusion of heterogeneous sensor modalities for the advancements of ADAS to autonomous vehicles","authors":"Pei-Jung Liang, Peter Chondro, Jheng-Rong Wu, Wei-Hao Lai, Yi-Fa Sun, Yi-Chen Lai, Tse-Min Chen","doi":"10.1109/VLSI-DAT.2018.8373245","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373245","url":null,"abstract":"The object detection technology is an essential aspect for the developments of the advanced driver-assistance systems (ADAS) and the autonomous driving vehicles (ADV). To achieve the standards of the developments, the state of the art should robustly achieve high accuracy and precision under various conditions (e.g. weather, illumination, exposures). This study proposes a sub-system framework that comprises of raw heterogeneous sensors fusion, hierarchical region of interest (ROI) detection with DCNN-based detectors, and decision fusion to provide rigorous and reliable object detection framework that can handle various spectra of driving environments. Experimental results have demonstrated the aimed purpose of the proposed framework.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs","authors":"Yutaka Adachi, C. Matsui, K. Takeuchi","doi":"10.1109/VLSI-DAT.2018.8373247","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373247","url":null,"abstract":"This paper proposes heterogeneously-integrated double asymmetric-latency storage class memories (SCMs) for SCM/NAND flash hybrid SSDs. Fast-Write SCM (W-SCM) achieves the fast write, while Fast-Read SCM (R-SCM) realizes the fast read. By the mix & match of two SCMs with asymmetric write/read latency, the performance of W-SCM/R-SCM/NAND flash hybrid SSD is improved by 86% compared with a conventional SCM/NAND flash hybrid S SD. The data management techniques for effectively controlling three types of memories, W-SCM, R-SCM and NAND flash, are implemented in the SSD controller. By changing the ECC strength and the maximum set/reset verify cycles of SCMs by the SSD controller, W-SCM and R-SCM are realized without changing circuits of SCMs.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory","authors":"Feng Zhang, Dongyu Fan, Qi-Peng Lin, Qiang Huo, Yun Li, Lan Dai, Chengying Chen, Haihua Shen","doi":"10.1109/VLSI-DAT.2018.8373268","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373268","url":null,"abstract":"Resistance switching random access memory (RRAM) is deemed as an emerging memory which has drawn considerable attention. This paper presents an approach for the synthesis of multilevel-cell (MLC) RRAM-based circuits using look-up-table (LUT) operations to complete a multiplication procedure. The recently proposed MLC function of RRAM revealed that RRAM could have a multilevel stable resistance by adjusting the voltage pulse, which is assigned to it. The simulation results show that the new LUT has a calculation speed that is increased by 35.7% and an area that is decreased by 14%, when compared with the traditional one for 16-bit multiplier.","PeriodicalId":257565,"journal":{"name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115512007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}