High-performance NTT architecture for large integer multiplication

Abstract

This paper presents an efficient architecture of number Theoretical transform (NTT), targeting at fulfilling large integer multiplication for fully homomorphic encryption applications. A systematic memory management scheme is proposed for the pipelined shared-memory NTT architecture implemented with mixed-radix multi-path delay commutators (MDCs). The presented data relocation scheme along with the MDC can be applied to merge multiple banks with single-port memory for further reducing the area requirement. Experimental results show that a 1,179,648-bit multiplier implemented by the proposed solution, including seamless data transfer among the building blocks, can lead to more than 39.8% area reduction with even a lower computational time as compared with the related works.