Proceedings of the 16th International Workshop on Data Management on New Hardware最新文献

Scalable and robust latches for database systems 用于数据库系统的可伸缩和健壮的锁存器

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-15 DOI: 10.1145/3399666.3399908

Jan Böttcher, Viktor Leis, Jana Giceva, Thomas Neumann, A. Kemper

引用次数: 13

Accelerating re-pair compression using FPGAs 利用fpga加速修复压缩

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-15 DOI: 10.1145/3399666.3399931

Robert Lasch, S. Demirsoy, Norman May, V. Ramamurthy, Christian Färber, K. Sattler

引用次数: 2

Variable word length word-aligned hybrid compression 可变字长字对齐混合压缩

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399935

Florian Grieskamp, Roland Kühn, J. Teubner

引用次数: 0

Empirical evaluation across multiple GPU-accelerated DBMSes 跨多个gpu加速dbms的经验评估

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399907

Hawon Chu, Seounghyun Kim, Joo-Young Lee, Young-Kyoon Suh

引用次数: 5

FPGA-Accelerated compression of integer vectors fpga加速整型向量的压缩

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399932

Mahmoud Mohsen, Norman May, Christian Färber, David Broneske

{"title":"FPGA-Accelerated compression of integer vectors","authors":"Mahmoud Mohsen, Norman May, Christian Färber, David Broneske","doi":"10.1145/3399666.3399932","DOIUrl":"https://doi.org/10.1145/3399666.3399932","url":null,"abstract":"An efficient compression of integer vectors is critical in dictionary-encoded column stores like SAP HANA to keep more data in the limited and precious main memory. Past research focused on lightweight compression techniques that trade low latency of data accesses for lower compression ratios. Consequently, only few columns in a wide table benefit from light-weight and effective compression schemes like run-length encoding, prefix compression or sparse encoding. Besides bit-packing, other columns remained uncompressed, which clearly misses opportunities for a better compression ratio for many columns. Furthermore, the main executor for compression was the CPU as compression involves heavy data transfer. Especially when used with co-processors, the data transfer overhead wipes out performance gains from co-processor usage. In this paper, we investigate whether we can achieve good compression ratios even for previously uncompressed columns by using binary packing and prefix suppression offloaded to an FPGA. As a streaming-processor, an FPGA is the perfect candidate to outsource the compression task. As a result of our OpenCL-based implementation, we achieve a saturation of the available PCIe bus during compression on the FPGA, by using less than a third the FPGA's resources. Furthermore, our real-world experiments against CPU-based SAP HANA shows a performance improvement of around a factor of 2 in compression throughput while compressing the data down to 60% of the best SAP HANA compression technique.","PeriodicalId":256784,"journal":{"name":"Proceedings of the 16th International Workshop on Data Management on New Hardware","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133595610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient generation of machine code for query compilers 有效的生成机器代码的查询编译器

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399925

Henning Funke, J. Mühlig, J. Teubner

引用次数: 9

Comparative analysis of OpenCL and RTL for sort-merge primitives on FPGA FPGA 上排序合并基元的 OpenCL 和 RTL 比较分析

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399897

Mehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May

引用次数: 6

nKV

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399934

Tobias Vinçon, Arthur Bernhardt, Ilia Petrov, Lukas Weber, Andreas Koch

引用次数: 16

Let's add transactions to FPGA-based key-value stores! 让我们将事务添加到基于fpga的键值存储中!

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399909

Z. István

{"title":"Let's add transactions to FPGA-based key-value stores!","authors":"Z. István","doi":"10.1145/3399666.3399909","DOIUrl":"https://doi.org/10.1145/3399666.3399909","url":null,"abstract":"In recent years we have seen a proliferation of FPGA-based key value stores (KVSs) [1--3, 5--7, 10] driven by the need for more efficient large-scale data management and storage solutions. In this context, FPGAs are useful because they offer network-bound performance even with small key-value pairs and near-data processing in a fraction of the energy budget of regular servers. Even though the first FPGA-based key-value stores started appearing already in 2013 and have evolved significantly in the meantime, almost no attention has been paid to offering transactions. Today, however, that such systems are becoming increasingly practical, we need to ensure consistency guarantees for concurrent clients (transactions). This position paper makes the case that adding transaction support is not particularly expensive, compared to other parts of these systems, and in the future all FPGA-based KVSs should provide some form of transactional guarantees. In the remaining of this paper we present a high level view of the typical pipelined architecture of FPGA-based KVSs that most existing designs follow, and show three different ways of implementing transactions, with increasing sophistication: from operation batching, through two phase locking (2PL), to a simplified snapshot isolation model.","PeriodicalId":256784,"journal":{"name":"Proceedings of the 16th International Workshop on Data Management on New Hardware","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123190470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Analyzing memory accesses with modern processors 用现代处理器分析内存访问

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI: 10.1145/3399666.3399896

Stefan Noll, J. Teubner, Norman May, Alexander Böhm

引用次数: 4