Comparative analysis of OpenCL and RTL for sort-merge primitives on FPGA

Proceedings of the 16th International Workshop on Data Management on New Hardware Pub Date : 2020-06-14 DOI:10.1145/3399666.3399897

Mehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May

引用次数: 6

Abstract

As a result of recent improvements in FPGA technology, their benefits for highly efficient data processing pipelines are becoming more and more apparent. However, traditional RTL methods for programming FPGAs require knowledge of digital design and hardware description languages. OpenCL™ provides software developers with a C-based platform for implementing their applications without deep knowledge of digital design. In this paper, we conduct a comparative analysis of OpenCL and RTL-based implementations of a novel heapsort with merging sorted runs. In particular, we quantitatively compare their performance, FPGA resource utilization, and development effort. Our results show that while requiring comparable development effort, RTL implementations of critical primitives used in the algorithm achieve 4X better performance while using half as much the FPGA resources.

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FPGA 上排序合并基元的 OpenCL 和 RTL 比较分析

随着 FPGA 技术的不断进步，其在高效数据处理流水线方面的优势正变得越来越明显。然而，对 FPGA 进行编程的传统 RTL 方法需要数字设计和硬件描述语言方面的知识。OpenCL™ 为软件开发人员提供了一个基于 C 语言的平台，无需深厚的数字设计知识即可实现其应用。在本文中，我们比较分析了 OpenCL 和基于 RTL 的新型堆排序实现，以及合并排序运行。特别是，我们定量比较了它们的性能、FPGA 资源利用率和开发工作量。我们的研究结果表明，在开发工作量相当的情况下，算法中使用的关键基元的 RTL 实现性能提高了 4 倍，而使用的 FPGA 资源仅为原来的一半。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 16th International Workshop on Data Management on New Hardware

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