13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems最新文献

Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS 在90纳米CMOS中实现的基于少数派3门和逆变器的存储元件

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-06-28 DOI: 10.1109/DDECS.2010.5491770

S. Aunet, Amir Hasanbegovic

引用次数: 3

A low phase noise 20 GHz voltage control oscillator using 0.18-μm CMOS technology 采用0.18-μm CMOS工艺的低相位噪声20ghz压控振荡器

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491788

Chia-Ming Yang, H. Kao, Y. C. Chang, M. T. Chen, H. M. Chang, C. H. Wu

引用次数: 8

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes LOS和LOC测试方案的功耗和过渡故障覆盖率分析

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491748

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, Junxia Ma, Wei Zhao, M. Tehranipoor, X. Wen

引用次数: 17

Synthesizing multiplier in reversible logic 可逆逻辑中的综合乘法器

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491757

Sebastian Offermann, R. Wille, G. Dueck, R. Drechsler

引用次数: 19

Advanced embedded memory testing: Reducing the defect per million level at lower test cost 高级嵌入式内存测试:以更低的测试成本降低每百万级别的缺陷

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491828

S. Hamdioui, A. V. Goor

{"title":"Advanced embedded memory testing: Reducing the defect per million level at lower test cost","authors":"S. Hamdioui, A. V. Goor","doi":"10.1109/DDECS.2010.5491828","DOIUrl":"https://doi.org/10.1109/DDECS.2010.5491828","url":null,"abstract":"Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of deviceparameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality. The objective of this embedded tutorial is to provide test engineers, memory and ASIC designers, researchers, students and managers with an overview of state-of-the art of fault models for SRAMs (including traditional fault modeling and recent development in fault models for current and future technologies), together with the latest test algorithms. Next, it describes test plans, which are shown to depend on the size of the SRAM, its speed, and the application domain. Thereafter, industrial results are used to show the effectiveness of the proposed algorithms and stresses. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.","PeriodicalId":256540,"journal":{"name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129360261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Synthesis of asynchronous monitors for critical electronic systems 关键电子系统异步监测器的合成

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491756

A. Porcher, K. Morin-Allory, L. Fesquet

引用次数: 2

Low-cost, customized and flexible SRAM MBIST engine 低成本，定制和灵活的SRAM MBIST引擎

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491749

A. V. Goor, Christian Jung, S. Hamdioui, G. Gaydadjiev

引用次数: 10

Ensuring high testability without degrading security: Embedded tutorial on “test and security” 确保高可测试性而不降低安全性:关于“测试和安全性”的嵌入式教程

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491831

G. D. Natale, M. Flottes, B. Rouzeyre

{"title":"Ensuring high testability without degrading security: Embedded tutorial on “test and security”","authors":"G. D. Natale, M. Flottes, B. Rouzeyre","doi":"10.1109/DDECS.2010.5491831","DOIUrl":"https://doi.org/10.1109/DDECS.2010.5491831","url":null,"abstract":"Cryptographic algorithms are used to protect sensitive information when the communication medium is not secure. Unfortunately, the hardware implementation of these cryptographic algorithms allows secret key retrieval using different forms of attacks based on the observation of key-related information: physical information (side-channel attacks), faulty behaviors (fault-based attacks), or internal states (DFT-based attacks) for instance. Dedicated design for security techniques have been proposed so far, ranging from the development of specific cell libraries to the implementation of extra functions for preventing the leakage of useful information for key identification. On the other hand, users can expect high quality product for secure applications and this expectation requires the development of test solutions for every component of the secure device. However, testing those devices faces a double dilemma: (i) how to test and, possibly, develop design-for-testability schemes providing high testability (high controllability/observability) while maintaining high security (no leakage), (ii) how to provide high security using dedicated design rules while maintaining high testability. This tutorial will address these issues presenting the security weaknesses generated by classical DFT techniques, pros and cons of security-dedicated DFT, BIST and Fault tolerance solutions, and impact of design for security techniques on testability","PeriodicalId":256540,"journal":{"name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Non-disjoint decomposition of logic functions in Reed-Muller spectral domain Reed-Muller谱域逻辑函数的不相交分解

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491764

E. Hrynkiewicz, S. Kolodzinski

引用次数: 5

SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures 探索异构架构的SystemC-AMS SDF模型综合

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2010-04-14 DOI: 10.1109/DDECS.2010.5491801

A. Popp, Andreas Herrholz, Kim Grüttner, Y. Moullec, P. Koch, W. Nebel

{"title":"SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures","authors":"A. Popp, Andreas Herrholz, Kim Grüttner, Y. Moullec, P. Koch, W. Nebel","doi":"10.1109/DDECS.2010.5491801","DOIUrl":"https://doi.org/10.1109/DDECS.2010.5491801","url":null,"abstract":"Cost efficient design of embedded HW/SW systems that need to meet certain requirements is a complex task due to the huge number of possible solutions, the ”design space”. Design space exploration methods depend on the designers' input in terms of application description, target architecture, and cost estimates for implementation alternatives. Obtaining feasible pre-implementation cost estimates causes lots of effort since the designer does not have confident information before implementation on the target architecture, or even different target architectures, has been performed. In this paper we present a methodology suitable for automatic cost estimation of synchronous data flow (SDF) graphs. We propose to start from an executable SystemC-AMS SDF specification, and demonstrate its automatic transformation and implementation for cost estimation on heterogeneous HW/SW architectures. The presented methodology allows the estimation of both HW and SW implementation alternatives of each SDF node based on a quick synthesis approach. These cost estimates are fed to a mapping framework to obtain a static binding and schedule for the architectures under exploration. With the proposed methodology the designer does not have to perform full synthesis and implementation for design space exploration. This is demonstrated by a case study of a Bluetooth baseband unit considered for implementation on a Xilinx Virtex-5 FPGA.","PeriodicalId":256540,"journal":{"name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123640034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1