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An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing 用于可重构计算的可重用IP核的XML模式
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806545
N. Rollins, A. Arnesen, M. Wirthlin
{"title":"An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing","authors":"N. Rollins, A. Arnesen, M. Wirthlin","doi":"10.1109/NAECON.2008.4806545","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806545","url":null,"abstract":"The reuse of intellectual property (IP) cores within reconfigurable computing systems is a promising approach for improving the productivity of reconfigurable system design. Further, there are a large variety of reusable IP cores available for a variety of application-specific functions. These cores, however, are created from different design tools and are difficult to integrate into a single reconfigurable system design. To facilitate the reuse of these cores, an XML schema has been created for representing the essential details of a core in a reconfigurable computing design environment. This paper presents this XML schema and describes how it can be used to facilitate reuse in reconfigurable computing systems.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114936999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Cognitive Information Processing in Face Recognition 人脸识别中的认知信息处理
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806564
Gorn Tepvorachai, Chris Papachristou, Frank Wolff, Robert Ewing
{"title":"Cognitive Information Processing in Face Recognition","authors":"Gorn Tepvorachai, Chris Papachristou, Frank Wolff, Robert Ewing","doi":"10.1109/NAECON.2008.4806564","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806564","url":null,"abstract":"In the conventional eigen face method, the principle component analysis (PCA) algorithm associates the eigen vectors with the changes in illumination. In this paper, we propose an improvement of facial image association for face recognition using a cognitive processing model. This method is based on the notion of multiple-phase associative memory. The Essex face database is used to verify our model for facial image recognition and compare the results of face recognition with conventional eigen face method. The simulation results show that the proposed cognitive processing model approach results in better performance than that of the conventional eigen face approach; while the computational complexity remains of the same magnitude as that of the eigen face method.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126146393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Disturbance Rejection in Approach and Landing Trajectory Generation for RLVs rlv进近与着陆轨迹生成中的干扰抑制
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806534
Zhesheng Jiang, R. Ordóñez
{"title":"Disturbance Rejection in Approach and Landing Trajectory Generation for RLVs","authors":"Zhesheng Jiang, R. Ordóñez","doi":"10.1109/NAECON.2008.4806534","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806534","url":null,"abstract":"Safety, reliability and operational costs play important roles in reusable launch vehicle (RLV) program. Our previous works proposed a scheme of motion primitives and neighboring optimal control to deal with on-board failure recovery for a RLV. In this paper, disturbance rejection for system parameters and winds is discussed. Robustification is mostly needed.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130045316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SCAN - Secure Processor SCAN -安全处理器
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806549
R. Kannavara, N. Bourbakis, A. Dollas, P. Athanas
{"title":"SCAN - Secure Processor","authors":"R. Kannavara, N. Bourbakis, A. Dollas, P. Athanas","doi":"10.1109/NAECON.2008.4806549","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806549","url":null,"abstract":"This paper presents the design of the SCAN secure processor. The SCAN secure processor is a modified SparcV8 processor architecture offering a SCAN-based encryption and decryption of 32 bit instructions and data. We further discuss the evaluation of the proposed SCAN-SP architecture with certain simulated benchmark applications.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126851104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Error Detection and Correction - A novel technique implementing Dual Rail Logic and Rollback recovery Architecture 错误检测与校正——一种实现双轨逻辑和回滚恢复架构的新技术
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806522
J. DeGroat, C. Ramswamy
{"title":"Error Detection and Correction - A novel technique implementing Dual Rail Logic and Rollback recovery Architecture","authors":"J. DeGroat, C. Ramswamy","doi":"10.1109/NAECON.2008.4806522","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806522","url":null,"abstract":"This paper investigates a computer architecture that provides fault detection in the execution elements, redundancy and error coding in memory storage elements, and incorporates software that allows rollback to a recovery boundary in the executing program when errors do occur. The architecture is intended for use in an environment where any errors encountered would be in the processors current computational instructions. The use of dual-rail logic is proposed for the purpose of providing single-bit error detection in computational units. This approach will be step towards creating a reliable computation environment in space based applications where the environment is quite hostile to computing systems.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"60 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123393305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Studies on Image Fusion Techniques for Dynamic Applications 面向动态应用的图像融合技术研究
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806562
D. Repperger, A. Pinkus, J. A. Skipper, R. Woodyard
{"title":"Studies on Image Fusion Techniques for Dynamic Applications","authors":"D. Repperger, A. Pinkus, J. A. Skipper, R. Woodyard","doi":"10.1109/NAECON.2008.4806562","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806562","url":null,"abstract":"A survey of present methods and current techniques being pursued by the US Air Force for image fusion and registration is conducted. Formulating the problem within a signal detection theory framework provides a unique thrust.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125271082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Classification of Application Development for FPGA-Based Systems 基于fpga系统的应用开发分类
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806547
Ivan Gonzalez, E. El-Araby, P. Saha, Tarek El-Ghazawi, Harald Simmler, S. Merchant, B. Holland, C. Reardon, Alan D. George, Herman Lam, Greg Stitt, N. Alam, Melissa C. Smith
{"title":"Classification of Application Development for FPGA-Based Systems","authors":"Ivan Gonzalez, E. El-Araby, P. Saha, Tarek El-Ghazawi, Harald Simmler, S. Merchant, B. Holland, C. Reardon, Alan D. George, Herman Lam, Greg Stitt, N. Alam, Melissa C. Smith","doi":"10.1109/NAECON.2008.4806547","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806547","url":null,"abstract":"Field-programmable gate arrays (FPGAs) have been used to accelerate DoD-related applications with promising performance. However, current development tools require significant hardware knowledge and are not amenable to the increasing complexity of FPGA-based systems. The application requirements are expected to change dramatically for future use cases, and require a well defined development methodology. This paper presents the results obtained after conducting an extensive survey and study about current FPGA tools. A classification for DoD use cases and FPGA tools is provided. This classification provides the current status of the available tools and identifies current tool limitations for DoD use cases.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133463324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Defense against Side-Channel Power Analysis Attacks on Microelectronic Systems 微电子系统侧信道功率分析攻击防御
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806536
V. Sundaresan, S. Rammohan, R. Vemuri
{"title":"Defense against Side-Channel Power Analysis Attacks on Microelectronic Systems","authors":"V. Sundaresan, S. Rammohan, R. Vemuri","doi":"10.1109/NAECON.2008.4806536","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806536","url":null,"abstract":"Side-channel power analysis attacks have become a potent threat to the security of embedded cryptographic devices in microelectronic systems. In this paper, we present an overview of the various side-channel power analysis attacks and defenses (countermeasures) against side-channel power analysis attacks. We introduce these countermeasures and present analyses based on security strength, ease of integration with EDA flows, and hardware characteristics like area, performance and power consumption. This paper is intended as a stepping stone towards developing more practical security-centric design methods that can be efficiently integrated with existing commercially viable designs and EDA flows, resulting in secure as well as hardware optimal implementations of side-channel power analysis attack resistant cryptographic devices.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Untethered On-The-Fly Radio Assembly With Wires-On-Demand 随需应变无线无线电组件
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806551
J. Surís, M. Shelburne, C. Patterson, P. Athanas, J. Bowen, T. Dunham, J. Rice
{"title":"Untethered On-The-Fly Radio Assembly With Wires-On-Demand","authors":"J. Surís, M. Shelburne, C. Patterson, P. Athanas, J. Bowen, T. Dunham, J. Rice","doi":"10.1109/NAECON.2008.4806551","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806551","url":null,"abstract":"In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing datapaths. We present the wires-on-demand framework that allocates a sandbox region in which modules from a library are flexibly placed and interconnected rapidly and autonomously in an embedded platform without vendor tools.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114154467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Robot Localization Using RE and Inertial Sensors 基于RE和惯性传感器的机器人定位
2008 IEEE National Aerospace and Electronics Conference Pub Date : 2008-07-16 DOI: 10.1109/NAECON.2008.4806569
M. Zmuda, A. Elesev, Y. Morton
{"title":"Robot Localization Using RE and Inertial Sensors","authors":"M. Zmuda, A. Elesev, Y. Morton","doi":"10.1109/NAECON.2008.4806569","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806569","url":null,"abstract":"A mobile robot must know its position in order to operate autonomously. The process of determining the robot's absolute position from sensor data is called robot localization. Sonar, inertial, RF, and laser sensors can all be used for navigation and localization purposes. These sensors can achieve good accuracy when operating in certain conditions. For example, sonar is useful when operating in a mapped environment containing known obstacles. Inertial sensors have trouble with drift, which is accentuated when moving continuously for long periods of time. By merging the results from multiple sensors, the accuracy over a wider range of conditions can be obtained. This work proposes a technique of merging heterogeneous signals from inertial and RF sensors. Since sensors have errors associated with their readings, the robot's state will be represented probabilistically. Based on the sensors used in this work, the robot's position, velocity, and acceleration will be estimated using a joint probability distribution function (PDF). At each time step, this PDF will be updated based on the RF readings and then updated again based on the readings from the inertial sensor. The proposed algorithm will be applied to simulation of an uncluttered, level environment. The accuracy of the localization algorithm is compared to the accuracies obtained by other localization algorithms. The results show better localization accuracy when using the RF and inertial sensors together.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121035349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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