Error Detection and Correction - A novel technique implementing Dual Rail Logic and Rollback recovery Architecture

J. DeGroat, C. Ramswamy
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引用次数: 2

Abstract

This paper investigates a computer architecture that provides fault detection in the execution elements, redundancy and error coding in memory storage elements, and incorporates software that allows rollback to a recovery boundary in the executing program when errors do occur. The architecture is intended for use in an environment where any errors encountered would be in the processors current computational instructions. The use of dual-rail logic is proposed for the purpose of providing single-bit error detection in computational units. This approach will be step towards creating a reliable computation environment in space based applications where the environment is quite hostile to computing systems.
错误检测与校正——一种实现双轨逻辑和回滚恢复架构的新技术
本文研究了一种计算机体系结构,该体系结构在执行元件中提供故障检测,在内存存储元件中提供冗余和错误编码,并包含了当错误发生时允许回滚到执行程序中的恢复边界的软件。该体系结构的目的是在处理器当前计算指令中遇到任何错误的环境中使用。为了在计算单元中提供单比特错误检测,建议使用双轨逻辑。这种方法将朝着在空间应用程序中创建可靠的计算环境迈出一步,而空间应用程序的环境对计算系统非常不利。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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