Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04.最新文献_第2页

Synchronous extensions to operation centric hardware description languages 以操作为中心的硬件描述语言的同步扩展

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459814

G. Nordin, J. Hoe

引用次数: 8

Formal verification of pipelined processors with precise exceptions 具有精确异常的流水线处理器的正式验证

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459832

Krishnamani Kalyanasundaram, R. Shyamasundar

引用次数: 0

Compositional verification for secure loading of smart card applets 为安全加载智能卡小程序而进行的组合验证

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459857

C. Sprenger, D. Gurov, M. Huisman

引用次数: 8

Designing a reorder buffer in Bluespec 在Bluespec中设计一个重排序缓冲区

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459823

Nirav H. Dave

引用次数: 18

Automated, compositional and iterative deadlock detection 自动，组成和迭代死锁检测

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459856

S. Chaki, E. Clarke, J. Ouaknine, N. Sharygina

{"title":"Automated, compositional and iterative deadlock detection","authors":"S. Chaki, E. Clarke, J. Ouaknine, N. Sharygina","doi":"10.1109/MEMCOD.2004.1459856","DOIUrl":"https://doi.org/10.1109/MEMCOD.2004.1459856","url":null,"abstract":"We present an algorithm to detect deadlocks in concurrent message-passing programs. Even though deadlock is inherently noncompositional and its absence is not preserved by standard abstractions, our framework employs both abstraction and compositional reasoning to alleviate the state space explosion problem. We iteratively construct increasingly more precise abstractions on the basis of spurious counterexamples to either detect a deadlock or prove that no deadlock exists. Our approach is inspired by the counterexample-guided abstraction refinement paradigm. However, our notion of abstraction as well as our schemes for verification and abstraction refinement differs in key respects from existing abstraction refinement frameworks. Our algorithm is also compositional in that abstraction, counterexample validation, and refinement are all carried out component-wise and do not require the construction of the complete state space of the concrete system under consideration. Finally, our approach is completely automated and provides diagnostic feedback in case a deadlock is detected. We have implemented our technique in the MAGIC verification tool and present encouraging results (up to 20 times speed-up in time and 4 times less memory consumption) with concurrent message-passing C programs. We also report a bug in the real-time operating system MicroC/OS version 2.70.","PeriodicalId":253853,"journal":{"name":"Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130273642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Checkers for SystemC designs SystemC设计的检查器

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459851

Daniel Große, R. Drechsler

{"title":"Checkers for SystemC designs","authors":"Daniel Große, R. Drechsler","doi":"10.1109/MEMCOD.2004.1459851","DOIUrl":"https://doi.org/10.1109/MEMCOD.2004.1459851","url":null,"abstract":"Today's complex systems are modeled on a high level of abstraction. In this context, C/C++-based description languages, like SystemC, become very important. The modeling features of SystemC enable adequate levels of abstraction, hardware/software integration and fast executable specifications. Using the SystemC design methodology, a system is partitioned into hardware and software. Then the modules are refined down to the implementation. Besides efficient modeling, the correct functional behavior is very important. Already today up to 80% of the overall design costs are due to verification. As the complete system cannot be formally verified, checking of the functional behavior during operation has to be considered. In this paper an approach is presented that allows to check temporal properties for a SystemC design not only during simulation, but also after fabrication inform of an on-line test. The method translates the properties into synthesizable SystemC instructions. By this, the properties can be checked like HDL assertions during simulation and after production since they can be synthesized together with the system. The proposed approach enables a concise circuit and system verification methodology.","PeriodicalId":253853,"journal":{"name":"Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Bluespec System Verilog: efficient, correct RTL from high level specifications Bluespec系统Verilog:高效，正确的RTL从高层次的规格

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459818

R. Nikhil

引用次数: 235

Formal methods and software reliability 形式化方法和软件可靠性

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Pub Date : 2004-06-23 DOI: 10.1109/MEMCOD.2004.1459838

G. Holzmann

引用次数: 49