2017 IEEE International Workshop on Signal Processing Systems (SiPS)最新文献_第5页

Task-based execution of synchronous dataflow graphs for scalable multicore computing 基于任务的同步数据流图执行，用于可扩展的多核计算

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110023

Georgios Georgakarakos, Sudeep Kanur, J. Lilius, K. Desnos

{"title":"Task-based execution of synchronous dataflow graphs for scalable multicore computing","authors":"Georgios Georgakarakos, Sudeep Kanur, J. Lilius, K. Desnos","doi":"10.1109/SiPS.2017.8110023","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8110023","url":null,"abstract":"Dataflow models of computation have early on been acknowledged as an attractive methodology to describe parallel algorithms, hence they have become highly relevant for programming in the current multicore processor era. While several frameworks provide tools to create dataflow descriptions of algorithms, generating parallel code for programmable processors is still sub-optimal due to the scheduling overheads and the semantics gap when expressing parallelism with conventional programming languages featuring threads. In this paper we propose an optimization of the parallel code generation process by combining dataflow and task programming models. We develop a task-based code generator for PREESM, a dataflow-based prototyping framework, in order to deploy algorithms described as synchronous dataflow graphs on multicore platforms. Experimental performance comparison of our task generated code against typical thread-based code shows that our approach removes significant scheduling and synchronization overheads while maintaining similar (and occasionally improving) application throughput.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125538206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Customizing fixed-point and floating-point arithmetic — A case study in K-means clustering 自定义定点和浮点算法- K-means聚类的案例研究

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109980

Benjamin Barrois, O. Sentieys

{"title":"Customizing fixed-point and floating-point arithmetic — A case study in K-means clustering","authors":"Benjamin Barrois, O. Sentieys","doi":"10.1109/SiPS.2017.8109980","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8109980","url":null,"abstract":"This paper presents a comparison between custom fixed-point (FxP) and floating-point (FlP) arithmetic, applied to bidimensional K-means clustering algorithm. After a discussion on the K-means clustering algorithm and arithmetic characteristics, hardware implementations of FxP and FlP arithmetic operators are compared in terms of area, delay and energy, for different bitwidth, using the ApxPerf2.0 framework. Finally, both are compared in the context of K-means clustering. The direct comparison shows the large difference between 8-to-16-bit FxP and FlP operators, FlP adders consuming 5–12 χ more energy than FxP adders, and multipliers 2–10χ more. However, when applied to K-means clustering algorithm, the gap between FxP and FlP tightens. Indeed, the accuracy improvements brought by FlP make the computation more accurate and lead to an accuracy equivalent to FxP with less iterations of the algorithm, proportionally reducing the global energy spent. The 8-bit version of the algorithm becomes more profitable using FlP, which is 80% more accurate with only 1.6 χ more energy. This paper finally discusses the stake of custom FlP for low-energy general-purpose computation, thanks to its ease of use, supported by an energy overhead lower than what could have been expected.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121527467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Obtaining an optimal set of head-related transfer functions with a small amount of measurements 用少量的测量获得一组最优的头部相关传递函数

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110008

Mikko Parviainen, Pasi Pertilä

引用次数: 1

CRN-based design methodology for synchronous sequential logic 基于crn的同步顺序逻辑设计方法

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109979

Zhiwei Zhong, Lulu Ge, Ziyuan Shen, X. You, Chuan Zhang

引用次数: 3

Processing LSTM in memory using hybrid network expansion model 使用混合网络扩展模型处理内存中的LSTM

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110011

Yu Gong, Tingting Xu, Bo Liu, Wei-qi Ge, Jinjiang Yang, Jun Yang, Longxing Shi

引用次数: 1

Successive cancellation decoder for very long polar codes 超长极性码的连续对消解码器

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110022

B. Gal, Camille Leroux, C. Jégo

{"title":"Successive cancellation decoder for very long polar codes","authors":"B. Gal, Camille Leroux, C. Jégo","doi":"10.1109/SiPS.2017.8110022","DOIUrl":"https://doi.org/10.1109/SiPS.2017.8110022","url":null,"abstract":"Polar codes are a family of error correcting codes that achieves the symmetric capacity of memoryless channels when the code length N tends to infinity. However, moderate code lengths are required in most of wireless digital applications to limit the decoding latency. In some other applications, such as optical communications or quantum key distribution, the latency introduced by very long codes is not an issue. The main challenge is to design codes with the best error correction capability, a tractable complexity and a high throughput. In such a context, SC decoding is an interesting solution because its performance improves with N while the computational complexity scales almost linearly. In this paper, we propose to improve the scalability of SC decoders thanks to four architectural optimizations. The resulting SC decoder is implemented on an FPGA device and favorably compares with state-of-the-art scalable SC decoders. Moreover, a 222 polar code SC decoder is implemented on a Stratix-5 FPGA. This code length is twice larger than the ones achieved in previous works. To the best of our knowledge, this is the first architecture for which a N = 4 million bits polar code can be actually decoded on a reconfigurable circuit.","PeriodicalId":251688,"journal":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Statistical analysis of Post-HEVC encoded videos 后hevc编码视频的统计分析

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110020

A. Jallouli, Fatma Belghith, M. A. B. Ayed, W. Hamidouche, J. Nezan, N. Masmoudi

引用次数: 5

Low complexity hardware accelerator for nD FastICA based on coordinate rotation 基于坐标旋转的nD - FastICA低复杂度硬件加速器

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110000

Swati Bhardwaj, Shashank Raghuraman, A. Acharyya

引用次数: 4

FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature 基于稀疏FIND特征的HDTV分辨率视频目标识别处理器的FPGA实现

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8109993

Yuri Nishizumi, Go Matsukawa, K. Kajihara, T. Kodama, S. Izumi, H. Kawaguchi, C. Nakanishi, Toshio Goto, Takeo Kato, M. Yoshimoto

引用次数: 5

Robust compressed analysis using subspace-based dictionary for ECG telemonitoring systems 基于子空间字典的心电远程监护系统鲁棒压缩分析

2017 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2017-10-01 DOI: 10.1109/SiPS.2017.8110016

Meng-Ya Tsai, Ching-Yao Chou, A. Wu

引用次数: 7