2019 IEEE International Superconductive Electronics Conference (ISEC)最新文献_第2页

Reconfigurable Logic Cell for Superconducting Magnetic Field Programmable Gate Array 超导磁场可编程门阵列的可重构逻辑单元

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990941

N. Katam, Haolin Cong, M. Pedram

{"title":"Reconfigurable Logic Cell for Superconducting Magnetic Field Programmable Gate Array","authors":"N. Katam, Haolin Cong, M. Pedram","doi":"10.1109/ISEC46533.2019.8990941","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990941","url":null,"abstract":"Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Series Arrays of Long Josephson Junctions Fabricated with a Focused Helium Ion Beam in YBa2Cu3O7-δ 聚焦氦离子束制备YBa2Cu3O7-δ长Josephson结系列阵列

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990938

J. LeFebvre, E. Cho, Kevin Pratt, S. Cybart

引用次数: 0

Dc-SQUID Readout with High Dynamic Range and Intrinsic MHz Frequency-Division Multiplexing Capability 具有高动态范围和固有MHz频分复用能力的Dc-SQUID读出器

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990966

D. Richter, A. Fleischmann, C. Enss, S. Kempf

引用次数: 1

Semi-Automated Design of Functional Elements for a New Approach to Digital Superconducting Electronics: Methodology and Preliminary Results 数字超导电子学新途径功能元件的半自动化设计:方法与初步结果

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990900

M. Frank, Rupert M. Lewis, N. Missert, M. Henry, M. Wolak, E. Debenedictis

{"title":"Semi-Automated Design of Functional Elements for a New Approach to Digital Superconducting Electronics: Methodology and Preliminary Results","authors":"M. Frank, Rupert M. Lewis, N. Missert, M. Henry, M. Wolak, E. Debenedictis","doi":"10.1109/ISEC46533.2019.8990900","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990900","url":null,"abstract":"In an ongoing project at Sandia National Laboratories, we are attempting to develop a novel style of superconducting digital processing, based on a new model of reversible computation called Asynchronous Ballistic Reversible Computing (ABRC). We envision an approach in which polarized flux-ons scatter elastically from near-lossless functional components, reversibly updating the local digital state of the circuit, while dissipating only a small fraction of the input fluxon energy. This approach to superconducting digital computation is sufficiently unconventional that an appropriate methodology for hand-design of such circuits is not immediately obvious. To gain insight into the design principles that are applicable in this new domain, we are creating a software tool to automatically enumerate possible topologies of reactive, undamped Josephson junction circuits, and sweep the parameter space of each circuit searching for designs exhibiting desired dynamical behaviors. But first, we identified by hand a circuit implementing the simplest possible nontrivial ABRC functional behavior with bits encoded as conserved polarized fluxons, namely, a one-bit reversible memory cell with one bidirectional I/O port. We expect the tool to be useful for designing more complex circuits.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124287560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Development of SQUID Amplifiers for Axion Search Experiments 轴子搜索实验用SQUID放大器的研制

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990953

S. Uchaikin, Y. Urade, S. Kono, M. Schmelz, R. Stolz, Yasunobu Nakamura, A. Matlashov, Doyu Lee, W. Chung, Seonjeong Oh, Y. Semertzidis, V. Zakosarenko, Ç. Kutlu, A. V. van Loo

引用次数: 3

Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics 超导数字电子器件中支持vlsi的EDA工具的进展

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990931

S. Whiteley, J. Kawa

引用次数: 6

qCDC: Metastability-Resilient Synchronization FIFO for SFQ Logic SFQ逻辑的亚稳态弹性同步FIFO

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990965

G. Datta, Haolin Cong, Souvik Kundu, P. Beerel

{"title":"qCDC: Metastability-Resilient Synchronization FIFO for SFQ Logic","authors":"G. Datta, Haolin Cong, Souvik Kundu, P. Beerel","doi":"10.1109/ISEC46533.2019.8990965","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990965","url":null,"abstract":"Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

[Copyright notice] (版权)

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/isec46533.2019.8990926

引用次数: 0

Development and Applications of a Four-Volt Josephson Arbitrary Waveform Synthesizer 四伏约瑟夫逊任意波形合成器的研制与应用

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990937

N. Flowers-Jacobs, A. Rüfenacht, A. Fox, S. Waltman, R. Schwall, J. Brevik, P. Dresselhaus, S. Benz

引用次数: 6

Layout versus Schematic with Design/Magnetic Rule Checking for Superconducting Integrated Circuit Layouts 超导集成电路布局与原理图的设计/磁规则检验

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990956

R. van Staden, J. Delport, J. A. Coetzee, C. Fourie

{"title":"Layout versus Schematic with Design/Magnetic Rule Checking for Superconducting Integrated Circuit Layouts","authors":"R. van Staden, J. Delport, J. A. Coetzee, C. Fourie","doi":"10.1109/ISEC46533.2019.8990956","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990956","url":null,"abstract":"The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2