2008 4th European Conference on Circuits and Systems for Communications最新文献

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Settling-time-oriented design procedure for two-stage amplifiers with current-buffer Miller compensation 带电流缓冲器米勒补偿的两级放大器的面向沉降时间的设计程序

2008 4th European Conference on Circuits and Systems for Communications Pub Date : 2008-07-10 DOI: 10.1109/ECCSC.2008.4611658

A. Pugliese, F. Amoroso, G. Cappuccino, G. Cocorullo

引用次数: 7

Boundary conditions for multi-tone steady-state analysis of nonlinear integrated analog circuits 非线性集成模拟电路多音稳态分析的边界条件

2008 4th European Conference on Circuits and Systems for Communications Pub Date : 2008-07-10 DOI: 10.1109/ECCSC.2008.4611669

L. Dumitriu, M. Iordache, G. Stamatescu

引用次数: 1

Networks on Chips: Scalable interconnects for future systems on chips 芯片上的网络:未来芯片上系统的可扩展互连

2008 4th European Conference on Circuits and Systems for Communications Pub Date : 2008-07-10 DOI: 10.1109/ECCSC.2008.4611685

Muhammad Ali, Michael Welzl, Martin. Zwicknagl, Muhammad Ali

{"title":"Networks on Chips: Scalable interconnects for future systems on chips","authors":"Muhammad Ali, Michael Welzl, Martin. Zwicknagl, Muhammad Ali","doi":"10.1109/ECCSC.2008.4611685","DOIUrl":"https://doi.org/10.1109/ECCSC.2008.4611685","url":null,"abstract":"According to the International Technology Roadmap for Semiconductors (ITRS), before the end of this decade we will be entering the era of a billion transistors on a single chip. It is being stated that soon we will have a chip of 50-100 nm comprising around 4 billion transistors operating at a frequency of 10 Ghz. Such a development means that in the near future we probably have devices with such complex functions ranging from mere mobile phones to mobile devices controlling satellite functions. But developing such kind of chips is not an easy task as the number of transistors increases on-chip, and so does the complexity of integrating them. Todaypsilas SoCs use shared or dedicated buses to interconnect the communicating on-chip resources. However, these buses are not scalable beyond a certain limit. In this case, the current interconnect infrastructure will become a bottleneck for the development of billion transistor chips. Hence, in this tutorial, we will try to highlight a new design paradigm that has been proposed to counter the inefficiency of buses in future SoCs. This new design paradigm has been termed with a variety of titles, but the most common and agreed upon one is networks on chips (NoCs). We will show that how this paradigm shift from ordinary buses to networks on chips can make the kind of SoCs mentioned above very much possible.","PeriodicalId":249205,"journal":{"name":"2008 4th European Conference on Circuits and Systems for Communications","volume":"487 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

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