2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献

Detecting intermittent resistive faults in digital CMOS circuits 数字CMOS电路中间歇性电阻性故障的检测

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-10-27 DOI: 10.1109/DFT.2016.7684075

Hassan Ebrahimi, Alireza Rohani, H. Kerkhoff

引用次数: 5

BTI aware thermal management for reliable DVFS designs BTI意识热管理可靠的DVFS设计

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-19 DOI: 10.1109/DFT.2016.7684059

H. Chahal, V. Tenentes, Daniele Rossi, B. Al-Hashimi

{"title":"BTI aware thermal management for reliable DVFS designs","authors":"H. Chahal, V. Tenentes, Daniele Rossi, B. Al-Hashimi","doi":"10.1109/DFT.2016.7684059","DOIUrl":"https://doi.org/10.1109/DFT.2016.7684059","url":null,"abstract":"In this paper, we show that dynamic voltage and frequency scaling (DVFS) designs, together with stress-induced BTI variability, exhibit high temperature-induced BTI variability, depending on their workload and operating modes. We show that the impact of temperature-induced variability on circuit lifetime can be higher than that due to stress and exceed 50% over the value estimated considering the circuit average temperature. In order to account for these variabilities in lifetime estimation at design time, we propose a simulation framework for the BTI degradation analysis of DVFS designs accounting for workload and actual temperature profiles. A profile is generated considering statistically probable workload and thermal management constraints by means of the HotSpot tool. Using the proposed framework we explore the expected lifetime of the Ethernet circuit from the IWLS05 benchmark suite, synthesized with a 32nm CMOS technology library, for various thermal management constraints. We show that margin-based design can underestimate or overestimate lifetime of DVFS designs by up to 67.8% and 61.9%, respectively. Therefore, the proposed framework allows designers to select appropriately the dynamic thermal management constraints in order to tradeoff long-term reliability (lifetime) and performance with upto 35.8% and 26.3% higher accuracy, respectively, against a temperature-variability unaware BTI analysis.","PeriodicalId":248988,"journal":{"name":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120937729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Efficient utilization of hierarchical iJTAG networks for interrupts management 高效利用分层iJTAG网络进行中断管理

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-19 DOI: 10.1109/DFT.2016.7684077

Ahmed M. Y. Ibrahim, H. Kerkhoff

{"title":"Efficient utilization of hierarchical iJTAG networks for interrupts management","authors":"Ahmed M. Y. Ibrahim, H. Kerkhoff","doi":"10.1109/DFT.2016.7684077","DOIUrl":"https://doi.org/10.1109/DFT.2016.7684077","url":null,"abstract":"Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for different reasons. For example, fault/event occurrences or measurement read-out requests; however iJTAG networks are inherently master/slave networks, where the instruments are the network slaves. In this work, a scalable interrupts-management methodology is presented for allowing instruments-initiated communication using hierarchical iJTAG networks. The presented method allows for an efficient access of the network according to the required use-case by allowing the network to be configured into a corresponding optimized mode. In addition, a novel on-chip localization methodology is presented, which significantly reduces the localization time of interrupting instruments as compared to previous works.","PeriodicalId":248988,"journal":{"name":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134242036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures 永久故障下多核混合临界系统的容错调度

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684070

Zaid Al-bayati, B. Meyer, Haibo Zeng

{"title":"Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures","authors":"Zaid Al-bayati, B. Meyer, Haibo Zeng","doi":"10.1109/DFT.2016.7684070","DOIUrl":"https://doi.org/10.1109/DFT.2016.7684070","url":null,"abstract":"Mixed-criticality systems are real-time systems that combine both safety-critical and non-critical applications. These systems have been gaining interest due to their practical applications and their adoption in standards in several domains. On the other hand, it is often overlooked in the research on mixed-criticality systems that these systems are still safety critical and must be able to operate even when the system's processors fail. In this paper, we present an approach to design multicore mixed-criticality systems that can survive permanent processor failures. Under the proposed work, critical tasks executing on the failing cores are migrated to other cores to allow them to continue execution. Space is made on the new cores by dropping non-critical tasks. Schedulability analysis is developed by extending the AMC-rtb analysis to support processor failures. The problem of finding a mixed-criticality system configuration on a multicore architecture is formulated as a Mixed Integer Linear Programming (MILP) problem. The MILP produces a system design that is schedulable on the underlying platform and tolerant to processor failures.","PeriodicalId":248988,"journal":{"name":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115477676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Guiding Genetic Algorithms using importance measures for reliable design of embedded systems 引导遗传算法在嵌入式系统可靠设计中的应用

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684069

H. Aliee, Stefan Vitzethum, M. Glaß, J. Teich, E. Borgonovo

引用次数: 7

In-place LUT polarity inVersion to mitigate soft errors for FPGAs 就地LUT极性反转以减轻fpga的软误差

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684074

J. Su, Ju-Yueh Lee, Chang Wu, Lei He

引用次数: 3

Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting 具有增强执行指纹识别的安全关键系统中的边界错误检测延迟

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684068

Mojing Liu, B. Meyer

引用次数: 4

Design and analysis of an approximate 2D convolver 二维近似卷积器的设计与分析

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684065

Ke Chen, F. Lombardi, Jie Han

引用次数: 4

Low cost resilient regular expression matching on FPGAs fpga的低成本弹性正则表达式匹配

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684073

Marcos T. Leipnitz, E. N. D. Souza, G. Nazar

{"title":"Low cost resilient regular expression matching on FPGAs","authors":"Marcos T. Leipnitz, E. N. D. Souza, G. Nazar","doi":"10.1109/DFT.2016.7684073","DOIUrl":"https://doi.org/10.1109/DFT.2016.7684073","url":null,"abstract":"The Network Function Virtualization (NFV) paradigm promises to make networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, Field-Programmable Gate Arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for FPGAs, soft errors on the configuration memory are a significant dependability threat. Therefore, in this work we evaluate the effects of configuration faults on the functionality of FPGA-based regular expression matching engines and propose fault tolerance mechanisms to improve its resilience against such faults.","PeriodicalId":248988,"journal":{"name":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121406374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Prognosis of NBTI aging using a machine learning scheme 基于机器学习方案的NBTI老化预测

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2016-09-01 DOI: 10.1109/DFT.2016.7684060

Naghmeh Karimi, K. Huang

引用次数: 12