Communicating Process Architectures Conference最新文献

{"title":"Virtual Machine Based Debugging for occam-pi","authors":"Carl G. Ritson, Jonathan Simpson","doi":"10.3233/978-1-58603-907-3-293","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-293","url":null,"abstract":"While we strive to create robust language constructs and design patterns which prevent the introduction of faults during software development, an inevitable element of human error still remains. We must therefore endeavor to ease and acceler- ate the process of diagnosing and fixing software faults, commonly known as debug- ging. Current support for debugging occam- programs is fairly limited. At best the developer is presented with a reference to the last known code line executed before their program abnormally terminated. This assumes the program does in fact termi- nate, and does not instead live-lock. In cases where this support is not sufficient, de- velopers must instrument their own tracing support, \"printf style\". An exercise which typically enlightens one as to the true meaning of concurrency... In this paper we ex- plore previous work in the field of debugging occam programs and introduce a new method for run-time monitoring of occam- applications, based on the Transterpreter virtual machine interpreter. By adding a set of extensions to the Transterpreter, we give occam- processes the ability to interact with their execution environment. Use of a virtual machine allows us to expose program execution state which would otherwise require non-portable or specialised hardware support. Using a model which bears sim- ilarities to that applied when debugging embedded systems with a JTAG connection, we describe debugging occam- by mediating the execution of one execution process from another.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127671482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Communicating Haskell Processes: Composable Explicit Concurrency using Monads","authors":"Neil C. C. Brown","doi":"10.3233/978-1-58603-907-3-67","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-67","url":null,"abstract":"Writing concurrent programs in languages that lack explicit support for concurrency can often be awkward and difficult. Haskell's monads provide a way to explicitly specify sequence and effects in a functional language, and monadic combi- nators allow composition of monadic actions, for example via parallelism and choice - two core aspects of Communicating Sequential Processes (CSP). We show how the use of these combinators, and being able to express processes as first-class types (monadic actions) allow for easy and elegant programming of process-oriented concurrency in a new CSP library for Haskell: Communicating Haskell Processes.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116442181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Designing Animation Facilities for gCSP","authors":"H. V. D. Steen, Marcel A. Groothuis, J. Broenink","doi":"10.3233/978-1-58603-907-3-447","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-447","url":null,"abstract":"To improve feedback on how concurrent CSP-based programs run, the graphical CSP design tool has been extended with animation facilities. The state of processes, constructs, and channel ends are indicated with colours both in the gCSP diagrams and in the composition tree (hierarchical tree showing the structure of the total program). Furthermore, the contents of the channels are also shown. In the Fringe session, we will present and demonstrate this prototype animation facility, being the result of the MSc project of Hans van der Steen, and ask for feedback.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130343051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA based Control of a Production Cell System","authors":"Marcel A. Groothuis, J. V. Zuijlen, J. Broenink","doi":"10.3233/978-1-58603-907-3-135","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-135","url":null,"abstract":"Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control software for this system is designed in gCSP using a reusable layered CSP based software structure. gCSP is extended with automatic Handel-C code generation for configuring the FPGA. Many motion control systems use floating point calculations for the loop controllers. Low \u0000cost general purpose FPGAs do not implement hardware-based floating point units. The loop controllers for this system are converted from floating point to integer based \u0000calculations using a stepwise refinement approach. The result is a complete FPGA based motion control system with better performance figures than previous CPU based \u0000implementations.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132159292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Two-Way Protocols for occam-pi","authors":"Adam T. Sampson","doi":"10.3233/978-1-58603-907-3-85","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-85","url":null,"abstract":"In the occam- programming language, the client-server communication pattern is generally implemented using a pair of unidirectional channels. While each channel's protocol can be specified individually, no mechanism is yet provided to indi- cate the relationship between the two protocols; it is therefore not possible to statically check the safety of client-server communications. This paper proposes two-way pro- tocols for individual channels, which would both define the structure of messages and allow the patterns of communication between processes to be specified. We show how conformance to two-way protocols can be statically checked by the occam- com- piler using Honda's session types. These mechanisms would considerably simplify the implementation of complex, dynamic client-server systems.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133453577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Visual Process-Oriented Programming for Robotics","authors":"Jonathan Simpson, Christian L. Jacobsen","doi":"10.3233/978-1-58603-907-3-365","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-365","url":null,"abstract":"When teaching concurrency, using a process-oriented language, it is often introduced through a visual representation of programs in the form of process network diagrams. These diagrams allow the design of and abstract reasoning about programs, consisting of concurrently executing communicating processes, without needing any syntactic knowledge of the eventual implementation language. Process network di- agrams are usually drawn on paper or with general-purpose diagramming software, meaning the program must be implemented as syntactically correct program code be- fore it can be run. This paper presents POPed, an introductory parallel programming tool leveraging process network diagrams as a visual language for the creation of process-oriented programs. Using only visual layout and connection of pre-created components, the user can explore process orientation without knowledge of the un- derlying programming language, enabling a \"processes first\" approach to parallel pro- gramming. POPed has been targeted specifically at basic robotic control, to provide a context in which introductory parallel programming can be naturally motivated.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"57 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120914882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Representation and Implementation of CSP and VCR Traces","authors":"Neil C. C. Brown, Marc L. Smith","doi":"10.3233/978-1-58603-907-3-329","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-329","url":null,"abstract":"Communicating Sequential Processes (CSP) was developed around a for- mal algebra of processes and a semantics based on traces (and failures and diver- gences). A trace is a record of the events engaged in by a process. Several program- ming languages use, or have libraries to use, CSP mechanisms to manage their con- currency. Most of these lack the facility to record the trace of a program. A standard trace is a flat list of events but structured trace models are possible that can provide more information such as the independent or concurrent engagement of the process in some of its events. One such trace model is View-Centric Reasoning (VCR), which offers an additional model of tracing, taking into account the multiple, possibly imper- fect views of a concurrent computation. This paper also introduces \"structural\" traces, a new type of trace that reflects the nested parallelism in a CSP system. The paper describes the automated generation of these three trace types in the Communicating Haskell Processes (CHP) library, using techniques which could easily be applied in other libraries such as JCSP and C++CSP2. The ability to present such traces of a concurrent program assists in understanding the behaviour of real CHP programs and for debugging when the trace behaviours are wrong. These ideas and tools promote a deeper understanding of the association between practicalities of real systems soft- ware and the underlying CSP formalism.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129776321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Critique of JCSP Networking","authors":"K. Chalmers, J. Kerridge, I. Romdhani","doi":"10.3233/978-1-58603-907-3-271","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-271","url":null,"abstract":"We present a critical investigation of the current implementation of JCSP Networking, examining in detail the structure and behavior of the current architecture. Information is presented detailing the current architecture and how it operates, and weaknesses in the implementation are raised, particularly when considering resource constrained devices. Experimental work is presented that illustrate memory and computational demand problems and an outline on how to overcome these weaknesses in a new implementation is described. The new implementation is designed to be lighter weight and thus provide a framework more suited for resource constrained devices which are a necessity in the field of ubiquitous computing.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128009239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process-Oriented Subsumption Architectures in Swarm Robotic Systems","authors":"Jeremy C. Posso, Adam T. Sampson, Jonathan Simpson, J. Timmis","doi":"10.3233/978-1-60750-774-1-303","DOIUrl":"https://doi.org/10.3233/978-1-60750-774-1-303","url":null,"abstract":"Previous work has demonstrated the feasibility of using process-oriented programming to implement simple subsumption architectures for robot control. However, the utility and scalability of process-based subsumption architectures for more complex tasks and those involving multiple robots has not been proven. We report our experience of applying these techniques to the implementation of a standard foraging problem in swarm robotics, using occam-π to implement a subsumption control system. Through building a system with a realistic level of complexity, we have discovered both advantages and disadvantages to the process-oriented subsumption approach for larger robot control systems.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121051155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling a Multi-Core Media Processor Using JCSP","authors":"A. Kosek, J. Kerridge, A. Syed","doi":"10.3233/978-1-58603-907-3-431","DOIUrl":"https://doi.org/10.3233/978-1-58603-907-3-431","url":null,"abstract":"Abstract. Manufacturers are creating multi-core processors to solve specialized problems. This kind of processor can process tasks faster by running them in parallel. This paper explores the usability of the Communicating Sequential Processes model to create a simulation of a multi-core processor aimed at media processing in hand-held mobile devices. Every core in such systems can have different capabilities and can generate different amounts of heat depending on the task being performed. Heat generated reduces the performance of the core. We have used mobile processes in JCSP to implement the allocation of tasks to cores based upon the work the core has done previously. Keywords. JCSP, multi-core processor, simulation, task allocation. Introduction Many manufacturers of semiconductor computer processors are designing multi-core systems these days [1]. In multi-core processing systems, allocation of work to processors can be seen as similar to the task of allocating work to people in a human society. A person responsible for controlling this process has to know the abilities of their employees and estimate the time in which a task can be finished. Tasks can often be finished faster if more workers are assigned to work on them. Generally, tasks can also be finished faster if they can be divided into smaller sub-tasks and sub-tasks can be processed concurrently. One very important condition that has to be met is that these sub-tasks have to be allocated wisely so that co-workers working on different sub-tasks can not hinder each other’s progress. The manager has to allocate the task to the worker that is the best for the assignment in current circumstances. Using this idea many contemporary scientists and engineers are building multi-core processing systems. Multi-core processor technology is one of the fastest developing hardware domains [2]. Modern personal computers already have multiple computing cores to increase a computer's performance. Multi-core systems for consumer electronics however have different challenges than those in personal computers. Targeted media processors have been a goal of research of many scientists. In paper [3] the authors are presenting a heterogeneous multiprocessor architecture designed for media processing. The multi-core architecture presented in [4] consist of three programmable cores specialized for frequently occurring media processing operations of higher complexity. Cores are fully programmable so they can be adapted to new algorithm developments in this field [4]. More advanced research was shown in [5] presenting heterogeneous multi-core processor capable of self reconfiguring to fit new requirements.","PeriodicalId":246267,"journal":{"name":"Communicating Process Architectures Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122771862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}