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Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference最新文献

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A functional memory type parallel processor for vector quantization 一种用于矢量量化的功能存储器型并行处理器
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600354
Kazutoshi Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, K. Tamaru
{"title":"A functional memory type parallel processor for vector quantization","authors":"Kazutoshi Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, K. Tamaru","doi":"10.1109/ASPDAC.1997.600354","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600354","url":null,"abstract":"We propose a memory-based parallel processor for vector quantization, called a functional memory type parallel processor for vector quantization (FMPP-VQ). It accelerates the nearest neighbour search of vector quantization. All distances between an input vector and reference vectors in a codebook are computed simultaneously in all PEs. The minimum value of all distances is searched in parallel. The nearest vector is obtained in O(k), where k stands for the dimension of vectors. An LSI including four PEs has been implemented. It operates at 25 MHz clock frequency.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117228281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VLSI Design and Education Center (VDEC) current status and future plan VLSI设计与教育中心(VDEC)现状与未来规划
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600210
K. Asada, K. Hoh
{"title":"VLSI Design and Education Center (VDEC) current status and future plan","authors":"K. Asada, K. Hoh","doi":"10.1109/ASPDAC.1997.600210","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600210","url":null,"abstract":"VDEC (VLSI Design and Education Center) is an inter-university center placed in the University of Tokyo, which has a mission to continuously promote and support VLSI education programs in Japanese universities, including the nationals and the privates. After briefly reviewing a history of VDEC, its functions and facilities are summarized, followed by future plans of chip implementation along with a network society.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129003934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-project chip activities in Korea-IDEC perspective 韩国- idec视角的多项目芯片活动
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600207
C. Kyung, I. Park, Ho-Jun Song
{"title":"Multi-project chip activities in Korea-IDEC perspective","authors":"C. Kyung, I. Park, Ho-Jun Song","doi":"10.1109/ASPDAC.1997.600207","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600207","url":null,"abstract":"This paper describes the current status of multi-project chip (MPC) services in Korea to promote full-custom and semi-custom IC design activities in universities. Although MPC foundry services for IC designs were started in a lesser scale more than 10 years ago, it is only recently that systematic and effective education has developed. The MPC foundry services program called IDEC (IC design education center) was launched with the planned support of the government and three major semiconductor companies in Korea. The paper introduces the activities of IDEC and other MPC foundry services.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hardware-software co-design: Tools for architecting systems-on-a-chip 硬件-软件协同设计:构建单片系统的工具
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600157
Rajaesh K. Gupta
{"title":"Hardware-software co-design: Tools for architecting systems-on-a-chip","authors":"Rajaesh K. Gupta","doi":"10.1109/ASPDAC.1997.600157","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600157","url":null,"abstract":"This paper examines the issues and progress in the design of highly integrated microelectronic systems. These microsystems rely on an array of diverse components such as processors, memory, network interfaces, graphics and DSP 'cores'. In particular, we discuss problems in the combined design of hardware and software for these systems. We present a decomposition of the co-design problem, and identify the needed technologies in specification/modeling, synthesis and validation for efficient and error-free system designs. Co-design tools along with domain-specific design methodologies provide a key advantage to the system integrator in building complex single-chip systems. We illustrate this point in the specific area of architectural evaluation using co-simulation tools.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A quantitative analysis for optimizing memory allocation 优化内存分配的定量分析
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600131
Youn-Sik Hong, C. Cho, D. Gajski
{"title":"A quantitative analysis for optimizing memory allocation","authors":"Youn-Sik Hong, C. Cho, D. Gajski","doi":"10.1109/ASPDAC.1997.600131","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600131","url":null,"abstract":"Memory allocation problem has two independent goals: minimization of number of memories and minimization of number of registers in one memory. Our concern is the ordering of bindings during memory allocation. We formulate and analyze three different memory allocation algorithms by changing their binding order. It is shown that when we combine these subtasks and solve them simultaneously by heuristic cost function significant savings (up to 20%) can be obtained in the total area of memories.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121195136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic synthesis for cellular architecture FPGAs using BDDs 基于bdd的蜂窝式fpga逻辑综合
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600136
Gueesang Lee
{"title":"Logic synthesis for cellular architecture FPGAs using BDDs","authors":"Gueesang Lee","doi":"10.1109/ASPDAC.1997.600136","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600136","url":null,"abstract":"In this paper, an efficient approach to the synthesis of CA (Cellular Architecture)-type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms, which can be mapped directly to the cell arrays are generated. In this approach, a BDD is modified so that each node of the BDD has another branch which is an exclusive-OR of the two branches of a node. Once the modified BDD is obtained, a traversal of the BDD is sufficient to generate the Maitra terms needed. Since a BDD can be traversed in O(n) steps, where it is the number of nodes in the BDD, Maitra terms are generated very efficiently. This also removes the need for generating minimal SOP or ESOP expressions which can be costly in some cases. The experiments show that the proposed method generates better results than existing methods.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126679278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure 基于有界切片网格结构的l形、t形和软块的总体平面规划
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600145
M. Kang, W. Dai
{"title":"General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure","authors":"M. Kang, W. Dai","doi":"10.1109/ASPDAC.1997.600145","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600145","url":null,"abstract":"A new method of non-slicing floorplanning is proposed, which is based on the new representation for non-slicing floorplans, called bounded slicing grid (BSG) structure. We developed a new greedy algorithm based on the BSG structure, running in linear time, to select the alternative shape for each soft block so as to minimize the overall area for general floorplan, including non-slicing structures. We propose a new stochastic optimization method, named genetic simulated annealing (GSA) for general floorplanning. Based on BSG structure, we extend SA-based local search and GA-based global crossover to L-shaped, T-shaped blocks and obtain high density packing of rectilinear blocks.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127023621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks 多层组合网络中确定素数蕴涵的AND/OR推理图
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600326
D. Stoffel, W. Kunz, Stefan Gerber
{"title":"AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks","authors":"D. Stoffel, W. Kunz, Stefan Gerber","doi":"10.1109/ASPDAC.1997.600326","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600326","url":null,"abstract":"This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtracking, BDDs). The paper shows how to build AND/OR reasoning graphs for arbitrary combinational circuits and proves basic theoretical properties of the graphs. It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits. In particular, the notions of prime implicants and permissible prime implicants are defined for multi-level circuits and it is proved that AND/OR reasoning graphs represent all these implicants. Experimental results are shown for PLA factorization.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115583296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
On the representational power of bit-level and word-level decision diagrams 论位级和字级决策图的表示能力
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600304
B. Becker, R. Drechsler, R. Enders
{"title":"On the representational power of bit-level and word-level decision diagrams","authors":"B. Becker, R. Drechsler, R. Enders","doi":"10.1109/ASPDAC.1997.600304","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600304","url":null,"abstract":"Several types of Decision Diagrams (DDs) have have been proposed in the area of Computer Aided Design (CAD), among them being bit-level DDs like OBDDs, OFDDs and OKFDDs. While the aforementioned types of DDs are suitable for representing Boolean functions at the bit-level and have proved useful for a lot of applications in CAD, recently DDs to represent integer-valued functions, like MTBDDs (=ADDs), EVBDDs, FEVBDDs, (*)BMDs, HDDs (=KBMDs), and K*BMDs, attract more and more interest, e.g., using *BMDs it was for the first time possible to verify multipliers of bit length up to n=256. In this paper we clarify the representational power of these DD classes. Several (inclusion) relations and (exponential) gaps between specific classes differing in the availability of additive and/or multiplicative edge weights and in the choice of decomposition types are shown. It turns out for example, that K(*)BMDs, a generalization of OKFDDs to the word-level, also \"include\" OBDDs, MTBDDs and (*)BMDs. On the other hand, it is demonstrated that a restriction of the K(*)BMD concept to subclasses, such as OBDDs, MTBDDs, (*)BMDs as well, results in families of functions which lose their efficient representation.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114888659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Enhancement of parallelism for tearing-based circuit simulation 基于撕裂电路仿真的并行性增强
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600314
K. Hachiya, Toshiyuki Saito, T. Nakata, N. Tanabe
{"title":"Enhancement of parallelism for tearing-based circuit simulation","authors":"K. Hachiya, Toshiyuki Saito, T. Nakata, N. Tanabe","doi":"10.1109/ASPDAC.1997.600314","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600314","url":null,"abstract":"A new circuit simulation system is presented with techniques \"Subcircuit Balancing with Estimated Update operation count\" (SBEU) and \"Asynchronous Distributed Row-based interconnection parallelization\" (A-DR). SBEU estimates Gaussian elimination cost of each subcircuit by counting number of update operations to achieve balanced circuit partitioning. A-DR makes it possible to overlap numerical operations and interprocessor communications in parallel Gaussian elimination of interconnection equations. On a 16-PE distributed memory parallel machine, an experimental simulation shows 9.9 times speedup over 1PE and distribution of the time consumed for each subcircuit is within /spl plusmn/26% deviation from the median.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1841 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129833784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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