2019 International Conference on Field-Programmable Technology (ICFPT)最新文献_第8页

Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern 基于合并交换排序的固定存储器访问模式离散高斯采样器

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00023

Shanquan Tian, Wen Wang, Jakub Szefer

{"title":"Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern","authors":"Shanquan Tian, Wen Wang, Jakub Szefer","doi":"10.1109/ICFPT47387.2019.00023","DOIUrl":"https://doi.org/10.1109/ICFPT47387.2019.00023","url":null,"abstract":"Discrete Gaussian samplers are used to sample integers from a discrete Gaussian distribution. Since this functionality is used in operations such as key generation, signing, or key encapsulation of lattice-based schemes, it is a fundamental building block of these cryptographic algorithms. One required feature of modern discrete Gaussian samplers when used in cryptographic algorithms is to be constant-time, to ensure security against timing side-channel attacks. Further, it is often desired to minimize potential for power or EM side-channel attacks by limiting how much information an attacker can gain from measuring power traces. To address the need for having a Gaussian sampler with these features in hardware, this paper presents a novel hardware implementation of a constant-time discrete Gaussian sampler with fixed memory access pattern realized on FPGAs. The design uses an approach based on Cumulative Distribution Table (CDT). Further, the new sampler uses a merge-exchange sort algorithm that enables generating the samples in batches. In the hardware, due to the use of the merge-exchange sort algorithm, the memory access pattern is always fixed, regardless of the values of the secret samples. This increases the resistance of the sampler to potential power or EM side-channel attacks as memory usage and accesses are independent of the secret values. The presented sampler can be fully parameterized at compile-time with the following Gaussian parameters: standard deviation, precision, and tail cut, generating a hardware design that matches the exact parameters required by the cryptographic algorithm. In addition, it can be parameterized, at compile-time, with the batch size for the number of samples to generate at a time. The design evaluation is based on synthesis data for various Xilinx FPGAs.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116888313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Automatic Generation of Application-Specific FPGA Overlays with RapidWright 使用RapidWright自动生成特定应用的FPGA覆盖

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00053

Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, C. Bobda

引用次数: 7

Amoeba-Inspired Hardware SAT Solver with Effective Feedback Control 具有有效反馈控制的变形虫启发的硬件SAT求解器

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00038

Anh Hoang Ngoc Nguyen, M. Aono, Yuko Hara-Azumi

引用次数: 8

Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs 基于fpga的高精度低精度深度神经网络训练

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00009

Sean Fox, Julian Faraone, D. Boland, K. Vissers, P. Leong

{"title":"Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs","authors":"Sean Fox, Julian Faraone, D. Boland, K. Vissers, P. Leong","doi":"10.1109/ICFPT47387.2019.00009","DOIUrl":"https://doi.org/10.1109/ICFPT47387.2019.00009","url":null,"abstract":"Low-precision training for Deep Neural Networks(DNN) has recently become a viable alternative to standard full-precision algorithms. Crucially, low-precision computation reduces both memory usage and computational cost, providing more scalability for Field Programmable Gate Arrays (FPGAs) with limited on-chip memory. In this paper, we describe and test a prototype training accelerator for Zynq All Programmable System on Chip (APSoC) devices using predominantly 8-bit integer numbers. Block floating-point quantisation and stochastic weight averaging techniques are applied during training toavoid any degradation in accuracy. Results of an implementation reveal memory savings and 17x speed-ups over processor only systems on several training tasks including the MNIST and CIFAR10 benchmarks, and online radio-frequency anomaly detection. Moreover, we propose modifications to the stochastic weight averaging low-precision (SWALP) algorithm to achieve a0.5% accuracy improvement for the abovementioned benchmarks with results within 0.1% of floating-point. We suggest that both inference and training can be deployed in the same package for stand-alone embedded applications.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"127 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE 快速DSE的时间约束高级综合性能估计器

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00063

A. B. Perina, J. Becker, Vanderlei Bonato

{"title":"Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE","authors":"A. B. Perina, J. Becker, Vanderlei Bonato","doi":"10.1109/ICFPT47387.2019.00063","DOIUrl":"https://doi.org/10.1109/ICFPT47387.2019.00063","url":null,"abstract":"The adoption of Field-Programmable Gate Array (FPGA) for general use in the High-Performance Computing scenario has been limited by its complex development flow required to get optimised designs coupled with a time-consuming compilation. High-Level Synthesis (HLS) tools are adopted to improve programmability, however the developer must perform several iterations of optimisation schemes in order to achieve reasonable performance results, which is tedious and not trivial. Several works employ Design Space Exploration (DSE) through different optimisation possibilities, coupled with fast performance estimators to avoid the unacceptable compilation times. This paper presents Lina, an expansion of the Lin-Analyzer fast peformance estimator for C/C++ HLS including timing-constrained scheduling and an extended analysis for nested loops. Results over the PolyBench benchmark show that the average relative error dropped from 8.85% to 3.02% when loop unrolling and pipelining directives were considered. As a result Lina becomes a better estimator for non-perfect loop nests and for different timing constraints, which can be adopted as an additional design space exploration knob.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127771672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Parallelization of Recursive Function in Ruby-Based High-Level Synthesis 基于ruby的高级合成中递归函数的并行化

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00079

R. Yamashita, Daichi Teruya, H. Nakajo

引用次数: 1

Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization 通过层次积量化加速近似近邻搜索

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00019

Ameer Abdelhadi, C. Bouganis, G. Constantinides

{"title":"Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization","authors":"Ameer Abdelhadi, C. Bouganis, G. Constantinides","doi":"10.1109/ICFPT47387.2019.00019","DOIUrl":"https://doi.org/10.1109/ICFPT47387.2019.00019","url":null,"abstract":"A fundamental recurring task in many machine learning applications is the search for the Nearest Neighbor in high dimensional metric spaces. Towards answering queries in large scale problems, state-of-the-art methods employ Approximate Nearest Neighbors (ANN) search, a search that returns the nearest neighbor with high probability, as well as techniques that compress the dataset. Product-Quantization (PQ) based ANN search methods have demonstrated state-of-the-art performance in several problems, including classification, regression and information retrieval. The dataset is encoded into a Cartesian product of multiple low-dimensional codebooks, enabling faster search and higher compression. Being intrinsically parallel, PQ-based ANN search approaches are amendable for hardware acceleration. This paper proposes a novel Hierarchical PQ (HPQ) based ANN search method as well as an FPGA-tailored architecture for its implementation that outperforms current state of the art systems. HPQ gradually refines the search space, reducing the number of data compares and enabling a pipelined search. The mapping of the architecture on a Stratix 10 FPGA device demonstrates over ×250 speedups over current state-of-the-art systems, opening the space for addressing larger datasets and/or improving the query times of current systems.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132250787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA 基于FPGA的100Gbps以太网键值存储高吞吐量低延迟分布式管理代理

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00034

Jinyu Xie, Yunhui Qiu, Wenbo Yin, Lingli Wang

{"title":"High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA","authors":"Jinyu Xie, Yunhui Qiu, Wenbo Yin, Lingli Wang","doi":"10.1109/ICFPT47387.2019.00034","DOIUrl":"https://doi.org/10.1109/ICFPT47387.2019.00034","url":null,"abstract":"Key-value store (KVS) is one of the most important NoSQL databases. To satisfy the demand for growing data in the era of big data, distributed KVS systems that enhance the scalability of storage systems are widely used in recent years. Hence, high-performance distributed management that implements functions such as data partitioning and message distribution is indispensable. In this paper, we present a high-throughput and low-latency distributed management proxy (DMP) for key-value store over 100Gbps Ethernet (100GbE). The proxy-based design which has flexibility and generality is fully implemented on FPGA. In the DMP, the consistent hashing algorithm is designed to partition KVS packets in pipeline. Then a hardware network offload engine is proposed to transmit network messages over 100GbE on FPGA to reduce the latency penalties caused by consistent hashing. Besides, in order to utilize the 100Gbps Ethernet bandwidth, four fully parallel and pipelined data paths are implemented in the DMP on an FPGA. The experimental results show that the peak throughput of the proposed DMP can reach 77.4 million queries per second (QPS), and the latency can achieve as low as 0.8µs for the small-size packets, which is 7.4x higher and 23x faster respectively than the software proxy implementation accelerated by Intel's DPDK.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132316062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs fpga上SPN推理的资源高效对数尺度算法

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00040

Lukas Weber, Lukas Sommer, J. Oppermann, Alejandro Molina, K. Kersting, A. Koch

引用次数: 5

An SoC-FPGA-Based Micro UGV with Localization and Motion Planning 基于soc - fpga的微型UGV定位与运动规划

2019 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2019-12-01 DOI: 10.1109/ICFPT47387.2019.00095

Yuya Kudo, A. Takada, Yuta Ishida, T. Izumi

{"title":"An SoC-FPGA-Based Micro UGV with Localization and Motion Planning","authors":"Yuya Kudo, A. Takada, Yuta Ishida, T. Izumi","doi":"10.1109/ICFPT47387.2019.00095","DOIUrl":"https://doi.org/10.1109/ICFPT47387.2019.00095","url":null,"abstract":"This paper presents a micro UGVs (Unmanned Ground Vehicles) using an SoC FPGA with self-localization and motion planning developed for the FPGA Design Competition. The purpose of this competition is to achieve external state recognition and vehicle control required for automatic driving with low power consumption and high performance using an FPGA. We adopt Xilinx Zynq UltraScale+ MPSoC and Xilinx Artix-7 for autonomous vehicles. The Zynq and Artix-7 are used for processing that requires high computational costs and processing that controls peripherals such as DC motors, respectively. An autonomous driving system is constructed with a layer structure from abstracted route planning to physical controlling. In the self-localization layer, high-precision estimation is performed by sensor fusion of landmark observations, wheel odometry, and inertial odometry using particle filter. In the path planning layer, a path is planned by Informed-RRT*, and in the path tracking layer, the vehicle is controlled to track the path by Pure Pursuit. A platform for implementing the autonomous driving system can be built with small amount of resources in the FPGAs. Our FPGA implementation of self-localization and motion planning are currently under development.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134559949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2