2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第8页

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation Cryo-CMOS传输量子比特控制器及其FPGA仿真验证

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774702

K. Tien, K. Inoue, S. Lekuch, D. Frank, S. Chakraborty, Pat Rosno, T. Fox, M. Yeck, J. Glick, R. Robertazzi, R. Richetta, J. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, R. Joshi, D. Underwood, Dorothy Wisnieff, C. Baks, D. Bethune, John Timmerwilke, B. Johnson, Brian P. Gaucher, D. Friedman

{"title":"A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation","authors":"K. Tien, K. Inoue, S. Lekuch, D. Frank, S. Chakraborty, Pat Rosno, T. Fox, M. Yeck, J. Glick, R. Robertazzi, R. Richetta, J. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, R. Joshi, D. Underwood, Dorothy Wisnieff, C. Baks, D. Bethune, John Timmerwilke, B. Johnson, Brian P. Gaucher, D. Friedman","doi":"10.23919/DATE54114.2022.9774702","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774702","url":null,"abstract":"Future generations of quantum computers are expected to operate in a paradigm where multi-qubit devices will predominantly perform circuits to support quantum error correction. Highly integrated cryogenic electronics are a key enabling technology to support the control of the large numbers of physical qubits that will be required in this fault-tolerant, error-corrected regime. Here, we describe our perspectives on cryoelectronics-driven qubit control architectures, and will then describe an implementation of a scalable, low-power, cryogenic qubit state controller that includes a domain-specific processor and a SSB upconversion I/Q-mixer-based RF AWG. We will also describe an FPGA-based emulation platform that is able to closely reproduce the system intention, and which was used to verify different aspects of the ASIC system design in in situ transmon qubit control experiments.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115712600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Raw Filtering of JSON Data on FPGAs fpga上JSON数据的原始过滤

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.48550/arXiv.2205.05464

Tobias Hahn, Andreas Becher, S. Wildermann, J. Teich

{"title":"Raw Filtering of JSON Data on FPGAs","authors":"Tobias Hahn, Andreas Becher, S. Wildermann, J. Teich","doi":"10.48550/arXiv.2205.05464","DOIUrl":"https://doi.org/10.48550/arXiv.2205.05464","url":null,"abstract":"Many Big Data applications include the processing of data streams on semi-structured data formats such as JSON. A disadvantage of such formats is that an application may spend a significant amount of processing time just on unselectively parsing all data. To relax this issue, the concept of raw filtering is proposed with the idea to remove data from a stream prior to the costly parsing stage. However, as accurate filtering of raw data is often only possible after the data has been parsed, raw filters are designed to be approximate in the sense of allowing false-positives in order to be implemented efficiently. Contrary to previously proposed CPU-based raw filtering techniques that are restricted to string matching, we present FPGA-based primitives for filtering strings, numbers and also number ranges. In addition, a primitive respecting the basic structure of JSON data is proposed that can be used to further increase the accuracy of introduced raw filters. The proposed raw filter primitives are designed to allow for their composition according to a given filter expression of a query. Thus, complex raw filters can be created for FPGAs which enable a drastical decrease in the amount of generated false-positives, particularly for IoT workload. As there exists a trade-off between accuracy and resource consumption, we evaluate primitives as well as composed raw filters using different queries from the RiotBench benchmark. Our results show that up to 94.3% of the raw data can be filtered without producing any observed false-positives using only a few hundred LUTs.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114757760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

SyncLock: RF Transceiver Security Using Synchronization Locking SyncLock:使用同步锁定的射频收发器安全性

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774556

Alán Rodrigo Díaz Rizo, H. Aboushady, H. Stratigopoulos

引用次数: 1

Compatibility Checking for Autonomous Lane-Changing Assistance Systems 自动变道辅助系统的兼容性检查

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774616

P. Huang, Kai-Wei Liu, Zongying Li, Sanggu Park, E. Andert, Chung-Wei Lin, Aviral Shrivastava

引用次数: 1

JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption JANUS-HD:利用FSM的顺序性和逻辑混淆的综合灵活性来阻止SAT攻击，同时提供强大的腐败

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774729

Leon Li, A. Orailoglu

{"title":"JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption","authors":"Leon Li, A. Orailoglu","doi":"10.23919/DATE54114.2022.9774729","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774729","url":null,"abstract":"Logic obfuscation has been proposed as a counter-measure towards chip counterfeiting and IP piracy by obfuscating circuit designs with a key-controlled locking mechanism. However, the extensive output corruption of early key gate based logic obfuscation techniques has exposed them to effective SAT attacks. While current SAT resilient logic obfuscation techniques succeed in undermining the attack by offering near-trivial output corruption, they do so at the expense of a drastic reduction in functional and structural protection scope. In this work, we present JANUS-HD based on novel insights that succeed to deliver the heretofore elusive goal of simultaneously boosting corruptibility and foiling SAT attacks. JANUS-HD obfuscates an FSM through diverse FF configurations for different transitions with the overall configuration setting as the obfuscation secret. A key-controlled Hamming distance comparator controls the obfuscation status at the minimized number of entrance states identified through a custom graph partitioning algorithm. Reliance on the inherent state transition patterns extends the obfuscation benefits to non-entrance states without exposing any additional key space pruning trace. We leverage the flexibility of state encoding and equivalence-based FSM transformations to generate an obfuscated netlist at low overhead using standard synthesis tools. Finally, we present a scan chain crippling mechanism that delivers unfettered scan chain access while eradicating any key trace leakage in the scan mode, thus thwarting chosen-input attacks aimed at the Hamming distance comparator. We illustrate through experiments that JANUS-HD delivers obfuscation scope improvements of up to 45.5x over the state-of-the-art, establishing the first cost-effective solution to offer a broad yet attack-resilient obfuscation scope against supply chain threats.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Full-stack quantum computing systems in the NISQ era: algorithm-driven and hardware-aware compilation techniques NISQ时代的全栈量子计算系统:算法驱动和硬件感知的编译技术

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774643

Medina Bandic, Sebastian Feld, C. G. Almudever

引用次数: 12

Unsupervised Test-Time Adaptation of Deep Neural Networks at the Edge: A Case Study 边缘深度神经网络的无监督测试时间自适应:一个案例研究

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774580

K. Bhardwaj, James Diffenderfer, B. Kailkhura, M. Gokhale

{"title":"Unsupervised Test-Time Adaptation of Deep Neural Networks at the Edge: A Case Study","authors":"K. Bhardwaj, James Diffenderfer, B. Kailkhura, M. Gokhale","doi":"10.23919/DATE54114.2022.9774580","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774580","url":null,"abstract":"Deep learning is being increasingly used in mobile and edge autonomous systems. The prediction accuracy of deep neural networks (DNNs), however, can degrade after deployment due to encountering data samples whose distributions are differ-ent than the training samples. To continue to robustly predict, DNNs must be able to adapt themselves post-deployment. Such adaptation at the edge is challenging as new labeled data may not be available, and it has to be performed on a resource-constrained device. This paper performs a case study to evaluate the cost of test-time fully unsupervised adaptation strategies on a real-world edge platform: Nvidia Jetson Xavier NX. In particular, we adapt pretrained state-of-the-art robust DNNs (trained using data augmentation) to improve the accuracy on image classification data that contains various image corruptions. During this prediction-time on-device adaptation, the model parameters of a DNN are updated using a single backpropagation pass while optimizing entropy loss. The effects of following three simple model updates are compared in terms of accuracy, adaptation time and energy: updating only convolutional (Conv-Tune); only fully-connected (FC-Tune); and only batch-norm parameters (BN-Tune). Our study shows that BN-Tune and Conv-Tune are more effective than FC-Tune in terms of improving accuracy for corrupted images data (average of 6.6%, 4.97%, and 4.02%, respectively over no adaptation). However, FC-Tune leads to significantly faster and more energy efficient solution with a small loss in accuracy. Even when using FC-Tune, the extra overheads of on-device fine-tuning are significant to meet tight real-time deadlines (209ms). This study motivates the need for designing hardware-aware robust algorithms for efficient on-device adaptation at the autonomous edge.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124294037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNs 面向概率的人工神经网络近似计算方法

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774505

Pengfei Huang, Chenghua Wang, Ke Chen, Weiqiang Liu

引用次数: 1

CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer CacheRewinder:利用回写缓冲区撤销推测缓存更新

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774690

Jongmin Lee, Jun-Yeon Lee, Taeweon Suh, Gunjae Koo

{"title":"CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer","authors":"Jongmin Lee, Jun-Yeon Lee, Taeweon Suh, Gunjae Koo","doi":"10.23919/DATE54114.2022.9774690","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774690","url":null,"abstract":"Transient execution attacks are critical security threats since those attacks exploit speculative execution which is an essential architectural solution that can improve the performance of out-of-order processors significantly. Such attacks change cache state by accessing secret data during speculative executions, then the attackers leak the secret information exploiting cache timing side-channels. Even though software patches against transient execution attacks have been proposed, the software solutions significantly slow down the performance of a system. In this paper, we propose CacheRewinder, an efficient hardware-based defense mechanism against transient execution attacks. CacheRewinder prevents leakage of secret information by revoking the cache updates done by speculative executions. To restore the cache state efficiently, CacheRewinder exploits the underutilized write-back buffer space as the temporary storage for victimized cache blocks evicted during speculative executions. Hence, when speculation fails CacheRewinder can quickly restore the cache state using the victim blocks held in the write-back buffer. Our evaluation exhibits CacheRewinder can effectively defend against transient execution attacks. The performance overhead by CacheRewinder is only 0.6%, which is negligible compared to the unprotected baseline processor. CacheRewinder also requires minimal storage cost since it exploits unused write-back buffer entries as storage for evicted cache blocks.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126252191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

LiM-HDL: HDL-Based Synthesis for In-Memory Computing 内存计算中基于hdl的合成

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774627

Saman Froehlich, R. Drechsler

{"title":"LiM-HDL: HDL-Based Synthesis for In-Memory Computing","authors":"Saman Froehlich, R. Drechsler","doi":"10.23919/DATE54114.2022.9774627","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774627","url":null,"abstract":"HDLs are widely used in EDA for abstract specification and synthesis of logic circuits. Despite the popularity and the many benefits of HDL-based synthesis, it has not yet been performed for in-memory computing. Hence, there is a need to design a particular HDL which supplies efficient and compatible descriptions. In this paper, we enable HDL-based synthesis for the Programmable Logic-in-Memory (PLiM) computer architecture. We present LiM-HDL - a Verilog-based HDL - which allows for the detailed description of programs for in-memory computation. Having the description given in LiM-HDL, we propose a synthesis scheme which translates the description into PLiM programs, i.e. a sequence of resistive majority operations. This includes lexical and syntax analysis as well as preprocessing, custom levelization and a compiler. In our experiments, we show the benefits of LiM-HDL compared to classical Verilog-based synthesis. We show in a case-study that LiM-HDL can be used to implement programs with respect to constraints of specific applications such as edge computing in IoT, for which the PLiM computer is of particular interest and where low area is a key requirement. In our case-study, we show that we can reduce the number of ReRAM devices needed for the computation of an encryption module by 69%.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1