2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)最新文献

{"title":"Sensorless speed control of separately excited DC motor using neuro-fuzzy controller","authors":"R. Antar, A. Allu, Ahmed J. Ali","doi":"10.1109/ICECCPCE.2013.6998767","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998767","url":null,"abstract":"A neuro-fuzzy controller designed for sensorless speed control of DC motor is presented in this paper. Artificial Neural network is used to solve the problem of tuning a fuzzy logic controller. The neuro-fuzzy controller uses neural network learning technique for tuning membership functions and setting the rule base from the simple data provided to estimate the DC motor speed. The speed of DC motor is estimated based on armature current and terminal voltage sensors to overcome mechanical and physical problems associated with traditional speed sensor. The neuro-fuzzy controller is designed and trained as a model adaptive reference system method. The DC drive circuit is designed, evaluated and modelled by MatlabSimulink in the forward and reverse motoring operation modes, respectively. The DC drive system is simulated at different speed variation in steady state and dynamic operating conditions. The simulation results illustrate the effectiveness of the controller. The speed response has fast dynamic response and acceptable agreement between the actual, estimated and desired speed.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance monitoring and analysis of cloud computing environment","authors":"Niloofar Khanghahi, R. Ravanmehr","doi":"10.1109/ICECCPCE.2013.6998759","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998759","url":null,"abstract":"Cloud Computing is the next big step in the internet's improvement, which can provides everything to people as a Service, whenever and wherever they want, for many application. It also demonstrates a fundamental technology trends, and it is already apparent that it is reshaping IT processes and marketplace. The term of “moving to cloud” refers to an organization moving away from traditional operational models to updated and new models and organizations, which nowadays has been happened for many enterprises. The performance analysis of cloud environments is very important due to the progress and the popularity of cloud. The results of this analysis would be more serious considering the organizations' expectation for a huge increase in performance against cost paid, investments performed and huge change in their organizations. The purpose of this paper is to show an overall perspective on cloud analysis criteria and then with the help of simulation of number of scenarios, some of these criteria are analyzed.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115388341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programmable logic controller based design and implementation of multiple axes solar tracking system","authors":"O. Mahmood","doi":"10.1109/ICECCPCE.2013.6998742","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998742","url":null,"abstract":"The power generation using solar energy has been used widely many years ago due to fuel shortage and its low cost. In this paper, a design and implement of dual axis solar tracking system has been implemented using programmable logic controller (PLC). This proposed system, keeps the solar panels aligned with the sun during the sunrise hours, in order to maximize solar power extracted from the sun. In this work an open loop control systems been designed and carried out using PLC, and direct current motors for solar cell sun tracking. The tracking has done in two manners, that is, the usual daily sun tracking vertically, and the seasonal sun tracking horizontally. The second tracking technique, computes the difference in the day hours per year in four seasons, with the aid of PLC program, which is the solar time of the day hours or the sunrise hours of the day. After the system has completely installed a suitable measurement has been carried out for the fixed and moving solar panel. As compared with usual fixed panels, the power that has been obtained from the solar system is 38% better than the fixed technique.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124439867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wavenet-based dual-path congestion control routing mechanism","authors":"J. Abdul-Jabbar, Omar A. Hazim, Zena N. Abdulkader","doi":"10.1109/ICECCPCE.2013.6998735","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998735","url":null,"abstract":"The wide use of computer networks, such as Internet, and network related applications makes computer networks the most integral medium for information transfer. Due to the increase in load on computer networks, congestion problems in their links will occur. Thus, any additional use of those congested links in packet forwarding makes the problem be more severing so that network service will deteriorate with the increase of both packet loss and queuing delay. In this paper, a new routing mechanism called wavenet-based dual-path congestion control routing mechanism (WBDPCCRM) is proposed. This congestion control routing mechanism is based on adding a least congested shortest path in addition to the original OSPF path between any source-destination node-pair. These two paths run in parallel and share the loads that are offered by the nodes. The least congested shortest path is an adaptive path takes into account the congestion state of each network link while it determines forwarding paths that delivers packets from source to destination through it. During this process, the congested links are avoided by shortest path calculation since their cost values are scaled up locally. The second path uses in its computations some information about the congestion and loading states gathered from a network predictor called wavenet-based link status predictor (WBLSP). The results show that WBDPCCRM can succeed in eliminating network congestion for some load scenarios or at least it can minimize such congestion.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Channel estimation for walsh hadamard precoded OFDM/OQAM","authors":"Mohammed Al-Attraqchi, S. Boussakta","doi":"10.1109/ICECCPCE.2013.6998754","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998754","url":null,"abstract":"Orthogonal frequency division multiplexing with offset quadrature modulation (OFDM/OQAM) has many advantages over the conventional OFDM system. The precoding of the OFDM/OQAM with Walsh Hadamard transform (WHT) improves system ability to mitigate deep fades in frequency selective channels. However, the addition of the transform prevents the functionality of the existing channel estimation techniques. Therefore, this work introduces a new technique to estimate channel coefficients utilising preamble structure. The proposed preamble methods are based on different pilot distribution and enhanced pilots power. The required number of symbols for the estimation is minimized while maintaining reliable performance.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115371740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid power system for residential load","authors":"Majid S. M. Al-Hafidh, Mustafa H. Ibrahem","doi":"10.1109/ICECCPCE.2013.6998737","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998737","url":null,"abstract":"The residential load is one of the largest components of the electrical load in the Iraqi power system. We can supply a part of the residential loads by utilizing the renewable energies. Recent research's show that the applications of a hybrid power system is preferable to achieve this goal. The paper studied the possibility of supplying part of the residential load in the city of Mosul - at north of Iraq by using a hybrid renewable energy system. The paper obtains the optimal hybrid system components for various cases. HOMER software was used to find the optimal solution of the system that feeds the residential loads.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121966809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pipelined MIPS processor with cache controller using VHDL implementation for educational purposes","authors":"H. Mahmood, S. Omran","doi":"10.1109/ICECCPCE.2013.6998739","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998739","url":null,"abstract":"This research adopts the VHDL (Very high speed IC Hardware Description Language) design of a direct mapped cache controller for a pipelined MIPS (Microprocessor without Interlocked Pipeline Stages) processor. In this design, the instruction cache and data cache are separated and located in the CPU (Central Processing Unit) core. Write back policy is used while no replacement algorithm is required. After completing the cache controller design, it is combined with a pipelined MIPS processor and used in programs execution. These designs are synthesized using (Xilinx ISE Design Suite 13.4) and simulated using (Xilinx ISim simulator).","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131789604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid image compression based on polynomial and block truncation coding","authors":"G. AL-Khafaji","doi":"10.1109/ICECCPCE.2013.6998758","DOIUrl":"https://doi.org/10.1109/ICECCPCE.2013.6998758","url":null,"abstract":"In this paper, a simple hybrid lossy image compression system is introduced; it is based on a combination of two techniques that exploits the spatial domain efficiently of linear polynomial approximation model to decompose image signal followed by block truncation coding of two-level quantizer on the residue part of the image, which represents the error caused by applying polynomial approximation. Then, the compressed information encoded using a simple run length coding and Huffman coding techniques. The test results shown in this paper are promising in terms of high compression rate achieved due to integrates the flexibility of polynomial model in overcoming the limitations of extra overhead information required compared to traditional predictive, along with effectiveness of block truncation coding as a 1-bit quantizer moments preserving.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Workshop on: Designing techniques of electronic circuits using field programmable gate arrays","authors":"","doi":"10.1109/iceccpce.2013.6998777","DOIUrl":"https://doi.org/10.1109/iceccpce.2013.6998777","url":null,"abstract":"FPGAs are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system. They provide a number of compelling advantages over ASIC technologies. ASICs typically take months to fabricate and cost hundreds of thousands to millions of dollars to obtain the first device; FPGAs are configured in less than a second (and can often be reconfigured if a mistake is made) and cost anywhere from a few dollars to a few thousand dollars. These high costs, and the need for a proportionally higher return on investment, drive most digital design starts toward FPGA implementation.","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121303781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Abstracts of the accepted papers","authors":"Ahmed J. Ali, A. Allu, R. Antar","doi":"10.1109/iceccpce.2013.6998775","DOIUrl":"https://doi.org/10.1109/iceccpce.2013.6998775","url":null,"abstract":"Rural and remote sites electrification, where national grid is almost impossible because of cost and geographical hurdle, is nowadays an important market for renewable energy based electricity production systems. This paper presents analyzing wind data from 5 masts using Scilab programming software calculating power densities by relative and Weibull density function, and designing hybrid power system for two villages using HOMER software, calculating their installation and operation& maintenance cost. 2(1569808129), Mazin Rejab Khalil, \" Design Of an Interruptible Soft Core Processor System to Compute Discrete Cosine Transform of Audio Signals \", Iraq : (8-13). Abstract: Embedded design Techniques are effective tools for configuring a processor system on field programmable gate arrays that can be adapted to function according to the designer target. One of the most outstanding application is to accommodate the embedded designed system to deal with digital signal processing techniques to be used in different practical applications especially in speech and image processing fields. This paper introduces a design of a soft Embedded design Techniques are effective tools for configuring a processor system on field programmable gate arrays that can be adapted to function according to the designer target. One of the most outstanding application is to accommodate the embedded designed system to deal with digital signal processing techniques to be used in different practical applications especially in speech and image processing fields. This paper introduces a design of a soft core processor system configured on Spartan 3E field programmable Gate arrays slice using embedded design techniques, the system can process an interrupted audio signal by discrete cosine transform methodology. C language is used to program the soft core processor with enabling its floating point unit. The system performance is consolidated by adding external memories, interrupt controller and a timer to the hard ware part. The system performance is tested and compared with the results achieved by Matlab 10.1 version software 3(1569818855), Hussein Ibzar Zynal; Shawkat Mohammed Younis, \" Harmonic Current Reduction of Three-Phase Rectifier Based on Modified Line Injection Technique\", Iraq : (14-19). Abstract: This paper presents a modified line injection technique to reduce the input line current harmonics generated by three-phase AC/DC rectifiers. In conventional harmonic current injection method the optimum harmonic current reduction is obtained when (root mean square) (rms) value of the injection third harmonic current equals the DC load current. Therefore the power diode peak current is increased by 72 % compared to without injection case . This paper presents a modified line injection technique to reduce the input line current harmonics generated by three-phase AC/DC rectifiers. In conventional harmonic current injection method the optimum harmonic current reduction is obtained w","PeriodicalId":226378,"journal":{"name":"2013 International Conference on Electrical Communication, Computer, Power, and Control Engineering (ICECCPCE)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115019698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}