{"title":"Design-for-manufacturing features in nanometer processes - A reverse engineering perspective","authors":"D. James","doi":"10.1109/ASMC.2009.5155953","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155953","url":null,"abstract":"The first decade of the new millennium has seen the introduction of a suite of production disciplines known collectively as Design for Manufacturability (DFM). While there has been no formal definition of DFM, we can regard it broadly as the techniques used to co-optimise design, layout, and processing to reduce variability and improve manufacturing parameters, with the aim of increasing yield and reliability. Retrospectively, we can view design rule checking, and the dummy features used to improve CMP, as early forms of DFM.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115726933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TLS-Dicing - An innovative alternative to known technologies","authors":"Hans-Ulrich Zuhlke, G. Eberhardt, R. Ullmann","doi":"10.1109/ASMC.2009.5155947","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155947","url":null,"abstract":"Thermal-Laser-Separation (TLS) - Dicing is a fast, clean and cost effective alternative for common dicing technologies. The process uses thermal induced mechanical forces to separate brittle materials like Silicon, GaAs or others. Heating is done very well defined by the spot of a laser. For cooling is a water-spray used. The induced forces separate brittle materials by cleaving. Even though TLS is a two-step process, especially for thin wafers a significant higher throughput is possible compared to mechanical sawing and known laser technologies. The yield is increased due to reduced breakage as well as by a reduced street width. TLS-dicing permit a minimal cost of ownership. In this paper after a description of basic principle and properties of the process a comparison with other dicing technologies is done. The advantages and disadvantages of TLS-dicing will be discussed. The prototype system will be described as well as applications of special interest.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124260070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stefan Radloff, Mario Abravanel, Blane Rhoads, Dylan Steeg, P. van der Meulen, M. Petraitis
{"title":"First Wafer Delay and setup: How to measure, define and improve First Wafer Delays and setup times in semiconductor fabs","authors":"Stefan Radloff, Mario Abravanel, Blane Rhoads, Dylan Steeg, P. van der Meulen, M. Petraitis","doi":"10.1109/ASMC.2009.5155959","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155959","url":null,"abstract":"First Wafer Delay (FWD) has been identified as a barrier to reduced fab cycle time and increased equipment productivity. As such, initiatives to reduce first wafer delay have been proposed as a focal point for next generation semiconductor fabs, including both 450mm fabs as well as “300mm Prime” factories. FWD and Setup Time are major detractors for cycle time reduction, in particular for small lot manufacturing. The definition of FWD, causes, as well as methods for improving FWD are discussed, in addition to recommendations for future equipment and factory design.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124575283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. van Roijen, O. Gluchenkov, J. Willis, M. Hurley
{"title":"Application and control of Laser Anneal at the 65 and 45 nm node","authors":"R. van Roijen, O. Gluchenkov, J. Willis, M. Hurley","doi":"10.1109/ASMC.2009.5155986","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155986","url":null,"abstract":"The application of Laser Anneal to semiconductor manufacturing is shown to have advantages and challenges for process control. We discuss some results, the implications of the real-time control mechanism on the Ultratech anneal tool, the impact of patterning effects and the use of inline data to ensure the tool achieves the target anneal condition.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"14 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Delahaye, J. Baltzinger, L. Denis, S. Chantepie, P. Costaganna, G. Richou, S. Lariviere, F. Aonzo, S. Delabriere, F. Poli, C. Bru, J. Meyniel, F. Allais, V. Dureuil, P. Raffin, E. Rondey
{"title":"Edge and extreme edge wafer manufacturing on 200 mm wafer: Methodology, yield challenges, cost effective solutions, limitations","authors":"B. Delahaye, J. Baltzinger, L. Denis, S. Chantepie, P. Costaganna, G. Richou, S. Lariviere, F. Aonzo, S. Delabriere, F. Poli, C. Bru, J. Meyniel, F. Allais, V. Dureuil, P. Raffin, E. Rondey","doi":"10.1109/ASMC.2009.5155965","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155965","url":null,"abstract":"In this paper we present the methodology for the extreme edge of the wafer qualification for aluminium 0.22 µm embedded EEPROM technology, as Edge Exclusion has moved to 2 mm. Yield challenges, cost effective solutions for the yield edge detractors, process monitoring enhancement and limitations are investigated. We discussed through examples process uniformity for CMP (Chemical Mechanical Polishing), etch or litho processes that we have had to solve. Solutions and limitations are described for nitride residual during planarization process, spacer etch process, and shorts within connection module. Monitoring scheme is evaluated for different techniques with parameters as cost efficiency or time response. This grid has been applied to the monitoring of the improved process with a wide range of confidence level which corresponds to a real difficulty for monitoring the edge and extreme edge of the wafer.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hiroyuki Hayashi, M. Oomura, Naoki Ihata, Akihiro Shinkawa, F. Fan, Jufeng Li
{"title":"Detection of critical defects with E-beam technology for development and monitoring of advanced NAND processes","authors":"Hiroyuki Hayashi, M. Oomura, Naoki Ihata, Akihiro Shinkawa, F. Fan, Jufeng Li","doi":"10.1109/ASMC.2009.5155964","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155964","url":null,"abstract":"This paper describes the technique of using electron beam inspection (EBI) for the purpose of detecting critical yield-limiting defects in the development of advanced NAND processes. Signal to Noise analysis was conducted on a V1WCMP wafer of a NAND flash device to optimize e-beam conditions to obtain best sensitivity to DOI (Defect of Interest) detection. TEM analysis was performed to confirm detection of defects due to subtle and severe under-etch. Correlation of inspection results with split process conditions is demonstrated. Experiments were also carried out to determine the best inspection parameters to achieve highest throughput required for fast process development cycle time as well as production monitoring of advanced NAND flash memory manufacturing.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132096534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Role of new materials in enhancing productivity of semiconductor manufacturing equipment","authors":"J. Foggiato","doi":"10.1109/ASMC.2009.5155970","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155970","url":null,"abstract":"A variety of new materials and improvements on currently used materials is given to show how the manufacturing productivity of semiconductor equipment is enhanced. With an initial introduction of seals and their elastomers, the materials representing mechanical parts of the systems are reviewed. Through a number of newly developed manufacturing techniques, the mechanical parts' performance is improved yielding higher uptime and especially improved particle levels. It is noted that extended use of currently available materials is possible thus addressing the need for cost reduction of current equipment.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133786561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Maxim, R. Goss, J. Rothe, M. Drozda, D. Adhikari
{"title":"Manufacturing optimization improvements leveraging SEMI E94-1107","authors":"C. Maxim, R. Goss, J. Rothe, M. Drozda, D. Adhikari","doi":"10.1109/ASMC.2009.5155956","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155956","url":null,"abstract":"In 2007, SEMI's information and control committee approved a new version of SEMI E94 (E94-1107). This version relaxed the connection between carriers and control job for processing wafers and formally introduced a way to redirect material based on host requests after the beginning of processing. As simulations indicate, this new standard is impacting several fab performance indicators, including throughput, cycle time, yield, and Just-In-Time (JIT) customer response. This paper discusses possible use cases leveraging the new standard feature and the resulting performance improvements.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132751787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Appello, V. Tancorre, C. Suzor, M. Hall, S. Talluto, S. Kekare
{"title":"Advances on yield learning through concurrent evaluation of design and process data","authors":"D. Appello, V. Tancorre, C. Suzor, M. Hall, S. Talluto, S. Kekare","doi":"10.1109/ASMC.2009.5155984","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155984","url":null,"abstract":"This paper presents advances in methodologies and tools for yield learning which are concurrently exploiting design, test and process data. In our experiments, we demonstrated how to understand yield losses correlated with excessive power drawn from the chip during functional electrical test of wafers.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133626369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michal Avinun-Kalish, Omer Sagy, S. M. Im, C. Lee, Jaehyoung Oh, J. Lim, Chulhong Kim, Hyungwon Yoo
{"title":"Novel SEM based imaging using secondary electron spectrometer for enhanced voltage contrast and bottom layer defect review","authors":"Michal Avinun-Kalish, Omer Sagy, S. M. Im, C. Lee, Jaehyoung Oh, J. Lim, Chulhong Kim, Hyungwon Yoo","doi":"10.1109/ASMC.2009.5155988","DOIUrl":"https://doi.org/10.1109/ASMC.2009.5155988","url":null,"abstract":"The challenge of high quality SEM imaging of defects at the bottom of dense and high aspect ratio structures is addressed here. We present a method that leverages the natural voltage contrast developed along dense topographies, by amplifying the information from the bottom of dense structures, using a secondary electron spectrometric technique. This improves both the detection limits and the defect image quality helping to obtain the defect root cause.","PeriodicalId":225517,"journal":{"name":"2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117210128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}