Synthesis Lectures on Computer Architecture最新文献_第2页

Innovations in the Memory System 记忆系统的创新

Synthesis Lectures on Computer Architecture Pub Date : 2019-09-10 DOI: 10.2200/s00933ed1v01y201906cac048

R. Balasubramonian

引用次数: 8

Cache Replacement Policies Cache替换策略

Synthesis Lectures on Computer Architecture Pub Date : 2019-06-17 DOI: 10.2200/s00922ed1v01y201905cac047

Akanksha Jain, Calvin Lin

引用次数: 11

The Datacenter as a Computer: Designing Warehouse-Scale Machines, Third Edition 作为计算机的数据中心:设计仓库规模的机器，第三版

Synthesis Lectures on Computer Architecture Pub Date : 2018-10-24 DOI: 10.2200/S00874ED3V01Y201809CAC046

L. Barroso, Urs Hölzle, Parthasarathy Ranganathan

{"title":"The Datacenter as a Computer: Designing Warehouse-Scale Machines, Third Edition","authors":"L. Barroso, Urs Hölzle, Parthasarathy Ranganathan","doi":"10.2200/S00874ED3V01Y201809CAC046","DOIUrl":"https://doi.org/10.2200/S00874ED3V01Y201809CAC046","url":null,"abstract":"This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day. It discusses how these new systems treat the datacenter itself as one massive computer designed at warehouse scale, with hardware and software working in concert to deliver good levels of internet service performance. The book details the architecture of WSCs and covers the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. Each chapter contains multiple real-world examples, including detailed case studies and previously unpublished details of the infrastructure used to power Google's online services. Targeted at the architects and programmers of today's WSCs, this book provides a great foundation for those looking to innovate in this fascinating and important area, but the material will also be broadly interesting to those who just want to understand the infrastructure powering the internet. The third edition reflects four years of advancements since the previous edition and nearly doubles the number of pictures and figures. New topics range from additional workloads like video streaming, machine learning, and public cloud to specialized silicon accelerators, storage and network building blocks, and a revised discussion of data center power and cooling, and uptime. Further discussions of emerging trends and opportunities ensure that this revised edition will remain an essential resource for educators and professionals working on the next generation of WSCs.","PeriodicalId":22115,"journal":{"name":"Synthesis Lectures on Computer Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83752331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 123

Principles of Secure Processor Architecture Design 安全处理器架构设计原理“，

Synthesis Lectures on Computer Architecture Pub Date : 2018-10-18 DOI: 10.2200/S00864ED1V01Y201807CAC045

Jakub Szefer

{"title":"Principles of Secure Processor Architecture Design","authors":"Jakub Szefer","doi":"10.2200/S00864ED1V01Y201807CAC045","DOIUrl":"https://doi.org/10.2200/S00864ED1V01Y201807CAC045","url":null,"abstract":"With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.","PeriodicalId":22115,"journal":{"name":"Synthesis Lectures on Computer Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83535316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Compiling Algorithms for Heterogeneous Systems 异构系统的编译算法

Synthesis Lectures on Computer Architecture Pub Date : 2018-01-17 DOI: 10.2200/S00816ED1V01Y201711CAC043

Steven Bell, Jing Pu, James Hegarty, M. Horowitz

引用次数: 3

Transactional Memory 事务内存

Synthesis Lectures on Computer Architecture Pub Date : 2007-01-12 DOI: 10.1007/978-3-031-01719-3

J. Larus, Ravi Rajwar

引用次数: 111