{"title":"BIST Approach for testing Embedded Memory Blocks in System-on-Chips","authors":"Zhiquan Zhang, Zhiping Wen, Lei Chen","doi":"10.1109/CAS-ICTD.2009.4960791","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960791","url":null,"abstract":"This paper presents a built-in self-test (BIST) approach to test embedded memory blocks in configurable system-on-chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testing embedded memory blocks in Xilinx Virtexl-4 series SoCs by using an embedded FPGA core. The proposed approach tests RAMs operating in all of different sizes both in single-port and dual- port modes. The paper also has developed a parameterized VerilogHDL code which is portable and can be used to test embedded memories with minimal changes in any configurable SoCs.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaojing Hu, Zhengxiang Song, Jianhua Wang, Yingsan Geng, Wang Shen
{"title":"A Fast and Practical Algorithm for Absolute Dominators Searching","authors":"Xiaojing Hu, Zhengxiang Song, Jianhua Wang, Yingsan Geng, Wang Shen","doi":"10.1007/978-1-4471-4793-0_23","DOIUrl":"https://doi.org/10.1007/978-1-4471-4793-0_23","url":null,"abstract":"","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115150062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fin Actuator System Circuit Design and Simulation","authors":"Jin Gao, Jia-dong Xu, W. Gao, Xuewei Liu","doi":"10.1109/CAS-ICTD.2009.4960826","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960826","url":null,"abstract":"During the development process of airborne missile fin actuator system, there are some problems in simulation, particularly the absence of simulation models. In order to solve this problem, a 'top-down' design and simulation flow is put forward by using the system design and simulation software Matlab from Mathwork corp. and the VHDL-AMS simulation software System Vision from Mentor Graphic corp. To find the advantage of this methodology for analog system, this model developing method is also effective to describe the mixed-signal system's structure and action.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123135559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaojing Hu, Zhengxiang Song, Jianhua Wang, Yingsan Geng, Wang Shen
{"title":"Ant Colony Optimizations for Initialization of Synchronous Sequential Circuits","authors":"Xiaojing Hu, Zhengxiang Song, Jianhua Wang, Yingsan Geng, Wang Shen","doi":"10.1109/CAS-ICTD.2009.4960786","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960786","url":null,"abstract":"In this paper, the problem of initializing sequential circuits is present. Achieving generation the shortest sequence able to drive the circuit to a known state, regardless of the initial state, ant colony optimization (ACO) is proposed, which has been effective in combination optimization problems. In this work, sequence generation problem is described in searching over a large vector graph, it is appropriate to ACO. We describe one form of applying a modified Max Min Ant System (MMAS) to the initialization that includes a dynamical local heuristics and a recent proposal for the pheromone updating rule to improve performance of algorithm. The experimental results for ISCAS89 benchmark sequential circuits illustrate that the algorithm can achieve better results in terms of the number of initialized flip- flops and sequence length.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The SEU Cross Section Estimation in SRAM Induced by Protons of Space Environment","authors":"Xunying Zhang, Xubang Shen","doi":"10.1109/CAS-ICTD.2009.4960900","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960900","url":null,"abstract":"The main goal of this paper is to propose an approach to calculate proton induced SEU cross sections. The starting point is the RPP sensitive volume model and some reasonable assumptions. An approximate analytic calculational model is presented, by which the valid number of the heavy ions induced by the interaction of proton and Si nuclei will be obtained. Then, the saturated proton SEU cross section for the typical 6T SRAM can be calculated by using this number and the experimental data of heavy ions. The calculated proton SEU cross section is in good agreement with experiment results.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Stream-Mode Based HW/SW Co-Emulation System for SOC Test and Verification","authors":"A. Ruan, Y. Liao, P. Li, Y. Wang, W. Li","doi":"10.1109/CAS-ICTD.2009.4960771","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960771","url":null,"abstract":"With the growing System-on-a-chip (SOC) design complexity, SOC test and verification has become a major bottleneck. In this context, efficient and reliable test and verification system are requested for SOC design before a SOC is committed to production. HW/SW co-emulation system combing software simulation with hardware acceleration is one of dominant systems, where interrupt-based communication mechanism is usually utilized. However, communication overhead will be resulted from data exchange between hardware side and software side at every cycle. A stream-mode based HW/SW co-emulation system is proposed and presented in the paper. In the proposed system, software side sends stimulus data and receives response data continuously while hardware side is testing System-under-Test (SUT) and generating response data. Communication traffic is reduced due to only time spent on software executions with hardware executions, sending and receiving data implemented in parallel. Experiment result demonstrates that stream-based communication mechanism can improve communication throughput by more than 10 folds compared to interrupt-based communication mechanism.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114492449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Method for Optimum Test Point Selection and Fault Diagnosis Strategy for BIT of Avionic System","authors":"D. Song, Qiong Hu, Chuanqing Wang","doi":"10.1109/CAS-ICTD.2009.4960753","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960753","url":null,"abstract":"A method for optimum test point selection and the fault diagnosis strategy which is based on the fault message matrix and features of BIT is proposed. The fault message matrix is divided based on the weight of the test points The diagnosis strategy is determined using dividing the fault message matrix and the thought of detecting first and isolating next. Result shows that the optimum method is suitable for BIT to select the appropriate test points and fault diagnosis procedure. Besides, average numbers of test steps were reduced.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128214947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of High-Order Sigma-Delta Modulator for BIST of Mixed-Signal Integrated Circuits","authors":"Xiubin Sun, Yongle Xie, Shan Liu","doi":"10.1109/CAS-ICTD.2009.4960804","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960804","url":null,"abstract":"A method for design of high-order sigma-delta modulator is proposed to generate high-precision analog signals for Built-In-Self-Test (BIST) of mixed-signal integrated circuits. The noise transfer function of the sigma-delta modulator is achieved by the sigma-delta toolbox. Using Determination Decision Diagram (DDD), symbolic transfer functions of the sigma-delta modulator are represented exactly and efficiently, and are applied to its coefficient quantization. The experiment on 4th-order sigma-delta modulator demonstrates that the in-band noise attenuation can also be kept to a maximum after quantization.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129918622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Virtual Frequency Characteristic Test Instrument Covered Mobile Communication Band","authors":"Jinjie Wang, Rui He, Xiao-hong Tang, Yu Yan","doi":"10.1109/CAS-ICTD.2009.4960906","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960906","url":null,"abstract":"In this paper, the principles and a new method to design a virtual frequency characteristic test instrument (VFCTI) system based on the \"Virtual Instrument\" theory are introduced. This VFCTI has distinct merits such as low cost, high accuracy, stable performance and small size. Then, circuit diagrams, the components we chose and photos of the whole system are offered to achieve main functions in hardware design. Design ideas and program flow are also given in software design. Meanwhile, it describes the primary functions and test analysis process of the panel, designed by CVI. Finally, it is proved to be an effective method to test frequency characteristic rapidly by testing some actual circuits, which will have bright applications in future.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114881765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A New Signal Capture Method Based on Real-Time Multi-Domain Trigger in Communication Analyzer","authors":"Xiao Yan, Qian Wang, Kaiyu Qin","doi":"10.1109/CAS-ICTD.2009.4960757","DOIUrl":"https://doi.org/10.1109/CAS-ICTD.2009.4960757","url":null,"abstract":"The typical signal characteristic capture method in multi-domain is discussed in a tutorial view. Since the typical signal characteristic capture method can't capture the whole signal which characteristics vary with time, a novel high efficiency architecture for signal characteristic capture based on real-time multi-domain trigger is proposed. Combined with the flexible cyclic trigger delay data storage mechanism, this signal characteristic capture method is implemented by FPGA in the communication signal analyzer. It's proved that the signal characteristic capture based on real-time multi-domain trigger can fast analyze the signal features in multi-domain, accurately identify the signal characteristic variance process, and trustily store the signal data for post analysis. So, it's quite suitable for burst modulated communication signal analysis.","PeriodicalId":218918,"journal":{"name":"2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126354112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}