S.H. Lee, Y. Kim, Y. Lee, H. Kang, C. Ahn, B. Kang, Jinju Lee, K. Cheng, Zhi Chen, K. Hess, J. Lyding
{"title":"Effect of low temperature deuterium annealing on plasma process induced damage","authors":"S.H. Lee, Y. Kim, Y. Lee, H. Kang, C. Ahn, B. Kang, Jinju Lee, K. Cheng, Zhi Chen, K. Hess, J. Lyding","doi":"10.1109/PPID.1999.798845","DOIUrl":"https://doi.org/10.1109/PPID.1999.798845","url":null,"abstract":"The effects of low temperature deuterium annealing on plasma process induced damage were examined for devices with a thin gate oxide. The devices were exposed to the plasma during poly-Si gate or metal processes, and the device characteristics were monitored by charge pumping and current-voltage measurements. It was observed that the metal process induced more plasma damage than the poly-Si gate process. The deuterium (D/sub 2/) annealing had little effect on oxide damage, but it was very effective in reducing the interface damage. After D/sub 2/ annealing, the devices showed a very low level of interface states, and the strength to withstand electrical stress was also enhanced. To maximize D/sub 2/ annealing effects, it is suggested that the D/sub 2/ annealing should be conducted without any H/sub 2/ annealing.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126984217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast hot-carrier aging method of charging damage measurement","authors":"K.P. Cheung, E. J. Lloyd","doi":"10.1109/PPID.1999.798850","DOIUrl":"https://doi.org/10.1109/PPID.1999.798850","url":null,"abstract":"To monitor plasma-charging damage, it is well known that one must not overlook the latent defects that are created by the damage but are not readily observable by most commonly used measurement methods. These latent defects are either passivated defects due to temperature cycling after the defects are created, or simply due to charge detrapping that render the defects invisible to many measurements. The common way to reveal these latent defects is to look for accelerated degradation of device parameters under electrical stress. A common stressing method is uniform Fowler-Nordheim tunneling through the gate-oxide. A less often used method is channel hot-carrier stress (Hook et al., Proc. P2ID96, p. 164, 1996). In this paper, we have demonstrated the suitability of using very short hot-carrier stress time to monitor plasma charging damage without the use of a very high acceleration voltage. When the stress is long enough to extract the lifetime from a large number of devices, the method allows us to find the intrinsic (damage free) lifetime of a particular transistor design. This ability to determine how much the devices are degraded quantitatively without the help of a reference device is unique among plasma-charging damage measurement methods.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"120 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Shin, W. Park, Ji-Soo Kim, C. Kang, T. Ahn, J. Moon, Moonyong Lee
{"title":"Suppression of topography dependent charging using a phase-controlled pulsed inductively coupled plasma","authors":"K. Shin, W. Park, Ji-Soo Kim, C. Kang, T. Ahn, J. Moon, Moonyong Lee","doi":"10.1109/PPID.1999.798837","DOIUrl":"https://doi.org/10.1109/PPID.1999.798837","url":null,"abstract":"The topography dependent charging (TDC) potential on the bottom of an oxide contact is measured with an in-situ charge-up monitoring wafer during plasma processing. The effects of the contact aspect ratio and the bias power on the TDC are investigated from the potentials measured on that wafer. By analyzing the potentials, we correlate the TDC to the difference of the charging potentials between a shading and a blank probe. We can suppress TDC considerably using a phase-controlled pulsed inductively coupled plasma, especially when the phase delay of the bias power relative to the source power is near 180/spl deg/ (out-of-phase condition).","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125588077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Siu, R. Patrick, V. Vahedi, S. Alba, G. Valentini, P. Colombo
{"title":"Effect of plasma density and uniformity, electron temperature, process gas, and chamber on electron shading damage","authors":"S. Siu, R. Patrick, V. Vahedi, S. Alba, G. Valentini, P. Colombo","doi":"10.1109/PPID.1999.798800","DOIUrl":"https://doi.org/10.1109/PPID.1999.798800","url":null,"abstract":"Electron shading is a major plasma process-induced device damage mechanism in high-density etching. Patrick et al (1997) showed that although gross plasma nonuniformity can cause damage, nonuniformities seen in modern commercial etchers contribute negligible damage. Vahedi et al. (1997) derived an analytic model that clarifies the contribution of plasma and device parameters to topography induced charging. Electron temperature and plasma density are the major damage parameters for plasma. Modeling and preliminary shading coefficient measurements show that plasma nonuniformity is indeed only a small contribution. Other major factors in plasma processing induced damage relate to the device, and are the gate oxide activation electric field, effective mass constant, and gate oxide thickness. Finally, topography dependent shading parameters need to be considered. These are a function of minimum line width, aspect ratio, and antenna ratio. Protection diodes and transient fuses (Krishnan et al., 1998) may help mitigate shading damage effects, but do not change the charging mechanism, namely electron shading. This work examines the role of plasma parameters on V/sub th/ shifts in transistors fabricated in a flash memory process where metal 1 and/or metal 2 were etched in either a Lam TCP/sup TM/ 9600SE or Lam TCP/sup TM/ 9600PTX chamber. The plasma parameters varied were plasma density, electron temperature, and plasma uniformity. The role of chamber gap height in the 9600SE was examined and the results compared to the those in the 9600PTX. The role of a lighter ion in decreasing damage as suggested by Tabara (1998) was also examined.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121841891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shoumian Chen, J. Sudijono, C. Perera, Ying Jin, F. Susilo, Xu Zeng, A.V. Kumar, J. Wen
{"title":"Plasma induced damage from HDP process on the ultra-thin gate oxide","authors":"Shoumian Chen, J. Sudijono, C. Perera, Ying Jin, F. Susilo, Xu Zeng, A.V. Kumar, J. Wen","doi":"10.1109/PPID.1999.798807","DOIUrl":"https://doi.org/10.1109/PPID.1999.798807","url":null,"abstract":"In general, as the gate oxide thickness scales down, plasma damage is reduced. In this paper, we show that, for a gate oxide thickness of 45 /spl Aring/, the plasma damage due to charging could still be severe, and that the damage may be induced by high-density plasma deposition in the back-end process of device fabrication rather than the traditional dry-etching process.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Stamper, J. Heidenreich, D.C. Hubanks, S. Luce, T. McDevitt
{"title":"Damascene copper integration","authors":"A. Stamper, J. Heidenreich, D.C. Hubanks, S. Luce, T. McDevitt","doi":"10.1109/PPID.1999.798841","DOIUrl":"https://doi.org/10.1109/PPID.1999.798841","url":null,"abstract":"The increase in ratio of wiring RC delay to the intrinsic transistor RC delay is motivating the IC industry to move from subtractive-aluminum to damascene-copper wiring. In addition to having 40% lower sheet resistance, damascene copper has significantly lower resistance and capacitance variability than subtractive-aluminum wiring due to improved reactive ion etch bias control. Damascene copper causes less plasma charging than subtractive-aluminum wiring in wire/via antenna devices and the charging can be modulated by electron shadowing during via RIE.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"382 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131857447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation and reduction of electron shading damage in high temperature etching","authors":"K. Nojiri, K. Kato, H. Kawakami","doi":"10.1109/PPID.1999.798801","DOIUrl":"https://doi.org/10.1109/PPID.1999.798801","url":null,"abstract":"The effect of wafer temperature on electron shading damage has been studied using an ECR plasma etcher. The gate oxide breakdown frequency was found to increase in proportion to exp(-E/kT), where E reflects the activation energy of Q/sub bd/. The electron shading damage in high temperature etching is dramatically reduced by reducing the ion saturation current and/or reducing the electron temperature. The effect of the small Q/sub bd/ at high temperature was found to be completely eliminated by changing the etching temperature from high to low before the open area clears. Consequently, the increase in the gate oxide failure at high temperature has been completely suppressed.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Charging protection and degradation by antenna environment on NMOS and PMOS transistors","authors":"J. Carrere, D.R. Heslinga","doi":"10.1109/PPID.1999.798844","DOIUrl":"https://doi.org/10.1109/PPID.1999.798844","url":null,"abstract":"Plasma induced damage from metal etch and HDP oxide deposition are investigated on CMOS structures for different antenna environments. Grounding the antenna environment provides a good protection for NMOS structures against both of these plasma processes, but is inefficient for PMOS structures. We explain this effect by applying electron-shading results to propose a new qualitative injection model.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Cha, E. Chor, H. Gong, A. Q. Zhang, Z. Dong, L. Chan
{"title":"Evaluation of rapid thermal nitrided ONO interpoly dielectric resistance to plasma process-induced damage","authors":"C. Cha, E. Chor, H. Gong, A. Q. Zhang, Z. Dong, L. Chan","doi":"10.1109/PPID.1999.798806","DOIUrl":"https://doi.org/10.1109/PPID.1999.798806","url":null,"abstract":"Investigative studies to improve the resistance to plasma process-induced damage and data-retention time of ONO in flash memory devices via a rapid thermal nitridation (RTN) process in N/sub 2/O ambient have been carried out. Experimental results revealed that an extra RTN step (1050/spl deg/C, 30 s) after nitride deposition during ONO growth indeed leads to a better quality stacked dielectric layer over the conventional process. Brief explanations of the beneficial effects of RTN are provided in this paper.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127689249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Downey, M. V. Malyshev, V. M. Donnelly, J. Colonell, N. Layadi, J. Yamartino, A. Paterson, H. Chen, P. Loewenhardt, D. Bohman, N. Singh
{"title":"Dependence of plasma damage on density and T/sub e/ in a decoupled plasma source metal etcher","authors":"S. Downey, M. V. Malyshev, V. M. Donnelly, J. Colonell, N. Layadi, J. Yamartino, A. Paterson, H. Chen, P. Loewenhardt, D. Bohman, N. Singh","doi":"10.1109/PPID.1999.798849","DOIUrl":"https://doi.org/10.1109/PPID.1999.798849","url":null,"abstract":"Plasma induced damage due to metal etch is a well established and well studied problem. Work by several groups has shown that the primary mechanism is electron shading, and that current injection through the gate oxide occurs during the period when open areas in the pattern have cleared but dense areas have not, leading to latent antenna effects (Krishnan et al., 1995; Kinoshita et al., 1997; Krishnan et al., 1997). It has also been shown that damage is generally more severe in high power processes, correlating generally with higher plasma density (Colonell et al., 1997; Tabara, 1996). This observation is easily explained by more available current, if the plasma can be viewed as a current limited source. Plasma damage in general is expected to become more severe with increasing electron temperature, but this effect is less well explored, due partly to the difficulty of measuring T/sub e/. In this paper, we examine the dependence of plasma damage on pressure during the overetch. Measurements of plasma density and T/sub e/ show that reduced damage at higher pressures correlates with a drop in both density and T/sub e/; applying a simple circuit model to the data suggests that decreased T/sub e/ is the primary driver.","PeriodicalId":217410,"journal":{"name":"1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133266477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}