2019 IEEE 4th International Verification and Security Workshop (IVSW)最新文献

Verification of Physical Chip Layouts Using GDSII Design Data 使用GDSII设计数据验证物理芯片布局

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854432

Aayush Singla, Bernhard Lippmann, H. Graeb

引用次数: 7

A Comprehensive Approach to a Trusted Test Infrastructure 可信测试基础结构的综合方法

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854428

Marc Merandat, Vincent Reynaud, E. Valea, J. Quévremont, Nicolas Valette, P. Maistri, R. Leveugle, M. Flottes, Sophie Dupuis, B. Rouzeyre, G. D. Natale

引用次数: 3

Two-Stage Architectures for Resilient Lightweight PUFs 弹性轻量级puf的两阶段架构

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854400

Haibo Su, Basel Halak, Mark Zwolinski

引用次数: 3

A Two-Flights Mutual Authentication for Energy-Constrained IoT Devices 能量受限物联网设备的两层互认证

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854438

Yıldıran Yılmaz, Basel Halak

引用次数: 4

Using Hardware Performance Counters to Detect Control Hijacking Attacks 使用硬件性能计数器检测控制劫持攻击

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854399

Miao Yu, Basel Halak, Mark Zwolinski

引用次数: 2

Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage 动态调整测试序列持续时间以提高功能覆盖率

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854389

Z. Takakis, Dimitrios Mangiras, C. Nicopoulos, G. Dimitrakopoulos

{"title":"Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage","authors":"Z. Takakis, Dimitrios Mangiras, C. Nicopoulos, G. Dimitrakopoulos","doi":"10.1109/IVSW.2019.8854389","DOIUrl":"https://doi.org/10.1109/IVSW.2019.8854389","url":null,"abstract":"The importance of functional coverage during frontend verification is steadily increasing. Complete coverage statistics, possibly spanning from block- to top-level, are required as a proof of verification quality and project development status. In this work, we present a coverage-driven verification methodology that relies on coverage-directed stimulus generation, with the goal being to increase functional coverage and decrease test application time. The test application time given to each one of the available constrained-random test sequences is dynamically adjusted by a feedback-based mechanism that observes online the quality of each applied test. The higher the quality, the more cycles are assigned to this test for future trials. Misbehaving test sequences are automatically replaced by new ones, in order to spend verification cycles on other tests that actually improve functional coverage. The proposed methodology is successfully applied to the register renaming sub-system of a 2-way superscalar out-of-order RISC-V processor. The results demonstrate both increased functional coverage and reduced test application time, as compared to a purely random approach.","PeriodicalId":213848,"journal":{"name":"2019 IEEE 4th International Verification and Security Workshop (IVSW)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124431572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Secure Design Flow of FPGA Based RISC-V Implementation 基于FPGA的RISC-V实现的安全设计流程

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854418

A. Siddiqui, G. Shirley, S. Bendre, Girija Bhagwat, J. Plusquellic, F. Saqib

引用次数: 9

Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection 利用逻辑锁定限制开关活动以改进基于功率分析的木马检测

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854402

Arash Nejat, Z. Kazemi, V. Beroulle, D. Hély, M. Fazeli

{"title":"Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection","authors":"Arash Nejat, Z. Kazemi, V. Beroulle, D. Hély, M. Fazeli","doi":"10.1109/IVSW.2019.8854402","DOIUrl":"https://doi.org/10.1109/IVSW.2019.8854402","url":null,"abstract":"Nowadays due to economic reasons most of the semiconductor companies prefer to outsource the manufacturing part of their designs to third fabrication foundries, the so-called fabs. Untrustworthy fabs can extract circuit blocks, the called intellectual properties (IPs), from the layouts and then pirate them. Such fabs are suspected of hardware Trojan (HT) threat in which malicious circuits are added to the layouts for sabotage objectives. HTs lead up to increase power consumption in HT-infected circuits. However, due to process variations, the power of HTs including few gates in million-gate circuits is not detectable in power consumption analysis (PCA). Thus, such circuits should be considered as a collection of small sub-circuits, and PCA must be individually performed for each one of them. In this article, we introduce an approach facilitating PCA-based HT detection methods. Concerning this approach, we propose a new logic locking method and algorithm. Logic locking methods and algorithm are usually employed against IP piracy. They modify circuits such that they do not correctly work without applying a correct key to. Our experiments at the gate level and post-synthesis show that the proposed locking method and algorithm increase the proportion of HT activity and consequently HT power to circuit power.","PeriodicalId":213848,"journal":{"name":"2019 IEEE 4th International Verification and Security Workshop (IVSW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129583388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the Reliability of the Ring Oscillator Physically Unclonable Functions 环形振荡器物理不可克隆函数的可靠性研究

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854401

Honorio Martín, E. Vatajelu, G. D. Natale, O. Keren

引用次数: 3

Electroforming-free Memristors for Hardware Security Primitives 用于硬件安全原语的免电铸记忆电阻器

2019 IEEE 4th International Verification and Security Workshop (IVSW) Pub Date : 2019-07-01 DOI: 10.1109/IVSW.2019.8854394

N. Du, M. Kiani, Xianyue Zhao, D. Bürger, O. Schmidt, R. Ecke, S. Schulz, H. Schmidt, I. Polian

引用次数: 3