System Verilog Assertions and Functional Coverage最新文献

筛选
英文 中文
Concurrent Assertions: Basics 并发断言:基础
System Verilog Assertions and Functional Coverage Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-24737-9_6
Ashok B. Mehta
{"title":"Concurrent Assertions: Basics","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_6","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_6","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Asynchronous FIFO Assertions 异步FIFO断言
System Verilog Assertions and Functional Coverage Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-24737-9_18
Ashok B. Mehta
{"title":"Asynchronous FIFO Assertions","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_18","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_18","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121123485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implications of Coverage Methodology 承保方法的影响
System Verilog Assertions and Functional Coverage Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-24737-9_27
Ashok B. Mehta
{"title":"Implications of Coverage Methodology","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_27","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_27","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121574717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
“assume” and “restrict” for Simulation and Formal (Static Functional) Verification 模拟和正式(静态功能)验证的“假设”和“限制”
System Verilog Assertions and Functional Coverage Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-24737-9_15
Ashok B. Mehta
{"title":"“assume” and “restrict” for Simulation and Formal (Static Functional) Verification","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_15","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_15","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130971637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clock Domain Crossing (CDC) Verification Using Assertions 时钟域交叉(CDC)验证使用断言
System Verilog Assertions and Functional Coverage Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-24737-9_16
Ashok B. Mehta
{"title":"Clock Domain Crossing (CDC) Verification Using Assertions","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_16","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_16","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128572122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信