{"title":"“assume” and “restrict” for Simulation and Formal (Static Functional) Verification","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_15","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":"101 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"System Verilog Assertions and Functional Coverage","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-030-24737-9_15","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}