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2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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V-band dual-conversion down-converter with low-doped N-well Schottky diode in 0.18 μm CMOS process 基于0.18 μm CMOS工艺的低掺杂n阱肖特基二极管v波段双转换下变频器
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569619
Yu-Chih Hsiao, C. Meng, H. Wei, Ta-Wei Wang, G. Huang, Mau-Chung Frank Chang
{"title":"V-band dual-conversion down-converter with low-doped N-well Schottky diode in 0.18 μm CMOS process","authors":"Yu-Chih Hsiao, C. Meng, H. Wei, Ta-Wei Wang, G. Huang, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2013.6569619","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569619","url":null,"abstract":"In this paper, a V-band dual-conversion down-converter with a silicon-based Schottky diode using low-doped N-well for DC and RF characteristics optimization is demonstrated in standard 0.18 μm CMOS technology. A triple-balanced subharmonic Schottky diode microwave mixer and a double-balanced resistive analog mixer are employed as the first conversion mixer and the second conversion mixer, respectively. As a result, the conversion gain is about -1 dB in the range of 45~64 GHz. The noise figure is about 20 dB, IP1dB is about -5 dBm and IIP3 is about 5 dBm. The total power consumption is 92.4 mW at 2.5 V supply voltage.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122713948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 240 GHz single-chip radar transceiver in a SiGe bipolar technology with on-chip antennas and ultra-wide tuning range 采用SiGe双极技术的240ghz单芯片雷达收发器，具有片上天线和超宽调谐范围
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569590
C. Bredendiek, N. Pohl, T. Jaeschke, K. Aufinger, A. Bilgic
{"title":"A 240 GHz single-chip radar transceiver in a SiGe bipolar technology with on-chip antennas and ultra-wide tuning range","authors":"C. Bredendiek, N. Pohl, T. Jaeschke, K. Aufinger, A. Bilgic","doi":"10.1109/RFIC.2013.6569590","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569590","url":null,"abstract":"This paper presents an ultra-wideband single-chip radar transceiver MMIC around 240 GHz in a SiGe:C bipolar laboratory technology with an fT of 240 GHz and fmax of 380 GHz. The presented transceiver architecture consists of a fundamental 120 GHz VCO, two 240 GHz frequency doublers, a fundamental 240 GHz down-conversion mixer, a divide-by-four stage, a PLL-mixer and two on-chip patch antennas. The complete transceiver architecture is fully differential. The chip facilitates a -1 dBm peak output power (EIRP) at the transmit patch antenna and a tuning range of 61 GHz. The phase noise at 1 MHz offset is -84 dBc/Hz at 240 GHz (and better than -76 dBc/Hz over the full tuning range). The 240 GHz mixer offers a simulated noise figure below 17 dB, a simulated conversion gain of better than 5 dB, and an input refered compression point of -1.3 dBm. The results are achieved with a power consumption of 750 mW from a single 5 V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133037321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A 32-Gbps 4×4 passive cross-point switch in 45-nm SOI CMOS 采用45nm SOI CMOS的32gbps 4×4无源交叉点开关
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569575
Donghyup Shin, Gabriel M. Rebeiz
{"title":"A 32-Gbps 4×4 passive cross-point switch in 45-nm SOI CMOS","authors":"Donghyup Shin, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2013.6569575","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569575","url":null,"abstract":"This paper presents a passive 4x4 cross-point switch in 45-nm SOI CMOS technology for LVDS systems with near-zero power consumption. The CMOS switch dimensions and layout structures are optimized using fullwave electromagnetic simulations for the highest 3-dB bandwidth in order to maximize the data-rate for digital signal transmission. Also, a novel series switch is used between the cells to enhance the bandwidth. The 4×4 switch matrix results in a measured 3-dB bandwidth of ~ 20 - 25 GHz (depending on the path) and an isolation > 40 dB at 26.5 GHz. The group delay variation is <; ±5 psec, and results in very low jitter as seen from eye measurements (<; 1.3 psec). Good eye-openings are obtained at 26 Gbps and up to 31.5 Gbps. The design is readily scalable to an 8×8 cross-point switch matrix.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A single chip HBT power amplifier with integrated power control 集成功率控制的单芯片HBT功率放大器
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569598
D. Ripley
{"title":"A single chip HBT power amplifier with integrated power control","authors":"D. Ripley","doi":"10.1109/RFIC.2013.6569598","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569598","url":null,"abstract":"The GSM power amplifier market continues to drive towards low cost and small size, but remains reluctant to compromise on performance. Current generation PA products utilize InGaP HBT to deliver RF performance and integrate bias and control on a supporting silicon die. This approach is common amongst many PA manufacturers with the exception of CMOS PA [1] solutions. This paper describes a solution using an HBT BiFET [2] technology to integrate both the precision control function and power amplifier onto a common die. The resulting solution opens opportunity for industry leading size and performance at no additional cost or RF performance penalty.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123736132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.5V 2.41GHz, 196.3dBc/Hz FoM differential colpitts VCO with an output voltage swing exceeding supply and ground potential requiring no additional inductor 一个0.5V 2.41GHz, 196.3dBc/Hz的FoM差分柯姆压控振荡器，输出电压摆幅超过电源和地电位，不需要额外的电感
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569516
Joo-Myoung Kim, S. Kim, Seok-Kyun Han, Sang-Gug Lee
{"title":"A 0.5V 2.41GHz, 196.3dBc/Hz FoM differential colpitts VCO with an output voltage swing exceeding supply and ground potential requiring no additional inductor","authors":"Joo-Myoung Kim, S. Kim, Seok-Kyun Han, Sang-Gug Lee","doi":"10.1109/RFIC.2013.6569516","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569516","url":null,"abstract":"A low-voltage differential Colpitts VCO that achieves an output voltage swing above the supply voltage and below the ground potential to improve the phase noise while requiring no additional inductor for a small chip area is proposed. Implemented in a 65nm CMOS process, the proposed VCO achieves the phase noise of -131.05dBc/Hz at an offset of 1MHz from an oscillation frequency of 2.41GHz and a FoM of 196.3dBc/Hz while dissipating 1.74mW from a 0.5V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125170981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A highly-linear CMOS RF programmable-gain driver amplifier with a digital-step differential attenuator for RF transmitters 一种高线性CMOS射频可编程增益驱动放大器，带有数字阶跃差分衰减器，用于射频发射机
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569629
Sunbo Shim, Bonhoon Koo, Songcheol Hong
{"title":"A highly-linear CMOS RF programmable-gain driver amplifier with a digital-step differential attenuator for RF transmitters","authors":"Sunbo Shim, Bonhoon Koo, Songcheol Hong","doi":"10.1109/RFIC.2013.6569629","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569629","url":null,"abstract":"This paper presents a CMOS RF programmable-gain driver amplifier (RF PGDA) for wireless transmitters. Digital-step differential attenuators precede a programmable-gain amplifier in order to enhance the dynamic range and to save power consumption, especially at low gain region. The RF PGDA fabricated in 0.13-μm CMOS technology with a 1.2 V supply voltage achieves a dynamic range of 49 dB with a step error of less than 0.5 dB and highly-linearized output satisfying the WCDMA/LTE specifications.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126302045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
245 GHz subharmonic receivers in SiGe SiGe中的245ghz次谐波接收机
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569533
Y. Mao, K. Schmalz, J. Borngräber, J. Scheytt, C. Meliani
{"title":"245 GHz subharmonic receivers in SiGe","authors":"Y. Mao, K. Schmalz, J. Borngräber, J. Scheytt, C. Meliani","doi":"10.1109/RFIC.2013.6569533","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569533","url":null,"abstract":"Two subharmonic receivers for 245 GHz spectroscopy sensor applications in the 245 GHz ISM band have been proposed. One receiver consists of an 2nd APDP (antiparallel diode pair) passive SHM (subharmonic mixer), a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA (power amplifier). The other consists of a single-ended four-stage CB (common base) LNA, an 2nd APDP passive SHM, an IF amplifier, a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA. The receivers are fabricated in a SiGe:C BiCMOS technology with fT/fmax=300/500 GHz. The measured conversion gain are -17 dB rsp. 10.6 dB at 245 GHz with 3-dB bandwidths of 13 GHz rsp. 14 GHz, and the single-side band noise figure are 17 dB rsp. 20 dB; the two receivers dissipates a power of 213 mW and 312 mW, respectively.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A low power 60-GHz 2.2-Gbps UWB transceiver with integrated antennas for short range communications 低功耗60ghz 2.2 gbps超宽带收发器，集成天线，用于短距离通信
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569587
A. Siligaris, F. Chaix, M. Pelissier, V. Puyal, J. Zevallos, L. Dussopt, P. Vincent
{"title":"A low power 60-GHz 2.2-Gbps UWB transceiver with integrated antennas for short range communications","authors":"A. Siligaris, F. Chaix, M. Pelissier, V. Puyal, J. Zevallos, L. Dussopt, P. Vincent","doi":"10.1109/RFIC.2013.6569587","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569587","url":null,"abstract":"A 60-GHz low power fully integrated transceiver including antennas, fabricated in CMOS 65nm SOI and packaged in low cost QFN is described. The circuit achieves 2 Gbps and 500 Mbps rates at 7.5 cm and 22.5 cm transmission ranges respectively. The transceiver energy efficiency is lower than 50 pJ/bit thanks to scalable power consumption using pulse generator and Super Regenerator Oscillator architecture.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122527101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
An automatically placed-and-routed ADPLL for the medradio band using PWM to enhance DCO resolution 一种自动放置和路由的ADPLL，用于无线频带，使用PWM来提高DCO分辨率
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569537
M. Faisal, D. Wentzloff
{"title":"An automatically placed-and-routed ADPLL for the medradio band using PWM to enhance DCO resolution","authors":"M. Faisal, D. Wentzloff","doi":"10.1109/RFIC.2013.6569537","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569537","url":null,"abstract":"An all-digital phase-locked loop for the MedRadio bands is presented. This ring oscillator based ADPLL was entirely designed and placed-and-routed using digital design flows and was fabricated in a 65 nm CMOS process. Pulse width modulation of the DCO control signals is introduced as a technique to improve the resolution of the DCO to 59 kHz/LSB. This ADPLL operates as a subsampling integer-N frequency synthesizer from 400 to 460 MHz, and consumes 2.1 mA from a 1 V supply, with an rms jitter of 13.3 ps.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131396997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A 45GHz CMOS transmitter SoC with digitally-assisted power amplifiers for 64QAM efficiency improvement 45GHz CMOS发射机SoC，带数字辅助功率放大器，可提高64QAM效率
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI: 10.1109/RFIC.2013.6569604
T. LaRocca, Yi-Cheng Wu, R. Snyder, J. Patel, K. Thai, C. Wong, Yeat Yang, L. Gilreath, Monte K. Watanabe, Hao Wu, Mau-Chung Frank Chang
{"title":"A 45GHz CMOS transmitter SoC with digitally-assisted power amplifiers for 64QAM efficiency improvement","authors":"T. LaRocca, Yi-Cheng Wu, R. Snyder, J. Patel, K. Thai, C. Wong, Yeat Yang, L. Gilreath, Monte K. Watanabe, Hao Wu, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2013.6569604","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569604","url":null,"abstract":"A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ modulator. A unique transformer splitting up converter drives eight parallel combined DAPAs. The chip is packaged in aluminum housing with WR22 outputs. A 64QAM signal achieves 1.8% EVM with 33dBc ACPR at 45GHz. The data rate is 450Mbps and the integrated output power exceeds -10dBm.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128384976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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