采用SiGe双极技术的240ghz单芯片雷达收发器,具有片上天线和超宽调谐范围

C. Bredendiek, N. Pohl, T. Jaeschke, K. Aufinger, A. Bilgic
{"title":"采用SiGe双极技术的240ghz单芯片雷达收发器,具有片上天线和超宽调谐范围","authors":"C. Bredendiek, N. Pohl, T. Jaeschke, K. Aufinger, A. Bilgic","doi":"10.1109/RFIC.2013.6569590","DOIUrl":null,"url":null,"abstract":"This paper presents an ultra-wideband single-chip radar transceiver MMIC around 240 GHz in a SiGe:C bipolar laboratory technology with an fT of 240 GHz and fmax of 380 GHz. The presented transceiver architecture consists of a fundamental 120 GHz VCO, two 240 GHz frequency doublers, a fundamental 240 GHz down-conversion mixer, a divide-by-four stage, a PLL-mixer and two on-chip patch antennas. The complete transceiver architecture is fully differential. The chip facilitates a -1 dBm peak output power (EIRP) at the transmit patch antenna and a tuning range of 61 GHz. The phase noise at 1 MHz offset is -84 dBc/Hz at 240 GHz (and better than -76 dBc/Hz over the full tuning range). The 240 GHz mixer offers a simulated noise figure below 17 dB, a simulated conversion gain of better than 5 dB, and an input refered compression point of -1.3 dBm. The results are achieved with a power consumption of 750 mW from a single 5 V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"A 240 GHz single-chip radar transceiver in a SiGe bipolar technology with on-chip antennas and ultra-wide tuning range\",\"authors\":\"C. Bredendiek, N. Pohl, T. Jaeschke, K. Aufinger, A. Bilgic\",\"doi\":\"10.1109/RFIC.2013.6569590\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an ultra-wideband single-chip radar transceiver MMIC around 240 GHz in a SiGe:C bipolar laboratory technology with an fT of 240 GHz and fmax of 380 GHz. The presented transceiver architecture consists of a fundamental 120 GHz VCO, two 240 GHz frequency doublers, a fundamental 240 GHz down-conversion mixer, a divide-by-four stage, a PLL-mixer and two on-chip patch antennas. The complete transceiver architecture is fully differential. The chip facilitates a -1 dBm peak output power (EIRP) at the transmit patch antenna and a tuning range of 61 GHz. The phase noise at 1 MHz offset is -84 dBc/Hz at 240 GHz (and better than -76 dBc/Hz over the full tuning range). The 240 GHz mixer offers a simulated noise figure below 17 dB, a simulated conversion gain of better than 5 dB, and an input refered compression point of -1.3 dBm. The results are achieved with a power consumption of 750 mW from a single 5 V supply.\",\"PeriodicalId\":203521,\"journal\":{\"name\":\"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"124 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2013.6569590\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2013.6569590","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 40

摘要

本文提出了一种采用SiGe:C双极实验室技术的240 GHz左右超宽带单片雷达收发器MMIC, fT为240 GHz, fmax为380 GHz。所提出的收发器架构由一个120 GHz基本压控振荡器、两个240 GHz倍频器、一个240 GHz基本下变频混频器、一个四分频级、一个锁相环混频器和两个片上贴片天线组成。完整的收发器架构是完全差分的。该芯片使发射贴片天线的峰值输出功率(EIRP)为-1 dBm,调谐范围为61 GHz。1mhz偏置时的相位噪声在240 GHz时为-84 dBc/Hz(在整个调谐范围内优于-76 dBc/Hz)。240 GHz混频器的模拟噪声值低于17 dB,模拟转换增益优于5 dB,输入参考压缩点为-1.3 dBm。该结果是在单个5v电源的功耗为750 mW的情况下实现的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 240 GHz single-chip radar transceiver in a SiGe bipolar technology with on-chip antennas and ultra-wide tuning range
This paper presents an ultra-wideband single-chip radar transceiver MMIC around 240 GHz in a SiGe:C bipolar laboratory technology with an fT of 240 GHz and fmax of 380 GHz. The presented transceiver architecture consists of a fundamental 120 GHz VCO, two 240 GHz frequency doublers, a fundamental 240 GHz down-conversion mixer, a divide-by-four stage, a PLL-mixer and two on-chip patch antennas. The complete transceiver architecture is fully differential. The chip facilitates a -1 dBm peak output power (EIRP) at the transmit patch antenna and a tuning range of 61 GHz. The phase noise at 1 MHz offset is -84 dBc/Hz at 240 GHz (and better than -76 dBc/Hz over the full tuning range). The 240 GHz mixer offers a simulated noise figure below 17 dB, a simulated conversion gain of better than 5 dB, and an input refered compression point of -1.3 dBm. The results are achieved with a power consumption of 750 mW from a single 5 V supply.
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