Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)最新文献_第4页

Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPU 基于多核CPU和GPU的无损检测超声重构并行化算法

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136904

Antoine Pedron, L. Lacassagne, F. Bimbard, S. Berre

引用次数: 2

Embedded operating systems energy overhead 嵌入式操作系统的能源开销

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136853

B. Ouni, C. Belleudy, S. Bilavarn, E. Senn

引用次数: 5

Optimization methodologies for complex FPGA-based signal processing systems with CAL 基于fpga的复杂信号处理系统的优化方法

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136878

A. Rahman, Hossam Amer, A. Prihozhy, Christophe Lucarz, M. Mattavelli

引用次数: 3

High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform 二维提升离散小波变换的高速VLSI结构

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136866

A. Darji, R. Bansal, S. Merchant, A. Chandorkar

{"title":"High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform","authors":"A. Darji, R. Bansal, S. Merchant, A. Chandorkar","doi":"10.1109/DASIP.2011.6136866","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136866","url":null,"abstract":"The lifting scheme reduces the computational complexity for computing Discrete Wavelet Transform (DWT) compared to convolution. We have proposed a high performance and memory efficient architecture with parallel scanning method for 2-D DWT using 5/3 Lifting wavelet. This 2-D architecture is composed with two 1-D DWT units and a Transpose Unit (TU). Proposed parallel scanning reduces requirement of on-chip line buffer compared to other line based scanning. Proposed 2-D DWT architecture utilizes only 2N size buffer for NxN sized image, which is low compare to 3.5N usual requirement for to implement 5/3 Lifting wavelet. This is achieved by performing column and row transform simultaneously. Designed 1-D DWT module can process two inputs at a time and produce two outputs per clock which reduces latency significantly compared to other 2-D dual scan based DWT architectures. Designed TU operates at half clock rate which reduces power and its design is independent of size of input image. Instead of shifter we propose Hardwired Scaling Unit (HSU) for coefficient multiplication. Unlike shift register unit this design saves clocks and helps in reducing power by great amount. This architecture is synthesized using Xilinx ISE 10.1 and is implemented on Virtex-IIPRO XC2VP30 FPGA. Very low FPGA resource utilization is found.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123872570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient maximal convex custom instruction enumeration for extensible processors 可扩展处理器的高效最大凸自定义指令枚举

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136868

Chenglong Xiao, E. Casseau

引用次数: 5

DFG implementation on multi GPU cluster with computation-communication overlap 计算通信重叠的多GPU集群DFG实现

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136859

Sylvain Huet, Vincent Boulos, V. Fristot, L. Salvo

引用次数: 4

An efficient parallel motion estimation algorithm and X264 parallelization in CUDA 一种高效的并行运动估计算法和CUDA中的X264并行化

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136860

Youngsub Ko, Youngmin Yi, S. Ha

{"title":"An efficient parallel motion estimation algorithm and X264 parallelization in CUDA","authors":"Youngsub Ko, Youngmin Yi, S. Ha","doi":"10.1109/DASIP.2011.6136860","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136860","url":null,"abstract":"H.264/AVC video encoders have been widely used for its high coding efficiency. Since the computational demand proportional to the frame resolution is constantly increasing, it has been of great interest to accelerate H.264/AVC by parallel processing. Recently, graphics processing units (GPUs) have emerged as a viable target for accelerating general purpose applications by exploiting fine-grain data parallelisms. Despite extensive research effort to use GPUs to accelerate the H.264/AVC algorithm, it has not been successful to achieve any speed-up over the x264 algorithm that is known as the fastest CPU implementation because of significant communication overhead between the host CPU and the GPU and intra-frame dependency in the algorithm. In this paper, we propose a novel motion estimation (ME) algorithm tailored for NVIDIA GPU implementation. It is accompanied by a novel pipelining technique, called sub-frame ME processing, to effectively hide the communication overhead between the host CPU and the GPU. The proposed H.264 encoder achieves more than 20% speed-up compared with x264.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"21 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120905395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Middleware approaches for adaptivity of Kahn Process Networks on Networks-on-Chip 片上网络上Kahn过程网络自适应的中间件方法

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136862

E. Cannella, O. Derin, T. Stefanov

引用次数: 7

A systemc TLM framework for distributed simulation of complex systems with unpredictable communication 具有不可预测通信的复杂系统分布式仿真的系统TLM框架

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136847

J. Peeters, N. Ventroux, Tanguy Sassolas, L. Lacassagne

引用次数: 14

Systemc modelization for fast validation of imager architectures 用于快速验证成像仪架构的系统建模

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136902

Y. Blanchard, A. Dupret, A. Peizerat

引用次数: 3