Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)最新文献

Design of a processor optimized for syntax parsing in video decoders 视频解码器中优化语法解析的处理器设计

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-02 DOI: 10.1109/DASIP.2011.6136850

Nicolas Siret, J. Nezan, Aimad Rhatay

引用次数: 2

Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach 基于HPAV通信协议的汽车分布式体系结构性能评估

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-02 DOI: 10.1109/DASIP.2011.6136848

Takieddine Majdoub, S. L. Nours, O. Pasquier, F. Nouvel

引用次数: 4

A framework for the design of reconfigurable fault tolerant architectures 可重构容错体系结构的设计框架

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-02 DOI: 10.1109/DASIP.2011.6136899

H. Pham, S. Pillement, O. Pasquier, S. L. Nours

引用次数: 1

Fast and accurate hybrid power estimation methodology for embedded systems 嵌入式系统快速准确的混合功率估计方法

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-02 DOI: 10.1109/DASIP.2011.6136852

S. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, J. Dekeyser

{"title":"Fast and accurate hybrid power estimation methodology for embedded systems","authors":"S. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, J. Dekeyser","doi":"10.1109/DASIP.2011.6136852","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136852","url":null,"abstract":"Nowadays, having the appropriate Electronic System Level (ESL) tools for power estimation in embedded systems is becoming mandatory. The main challenge for the design of such dedicated tools is to achieve a better trade-offs between accuracy and speed. In this paper, a new power consumption estimation methodology for embedded systems is proposed. First, the Functional Level Power Analysis (FLPA) is used to set up generic power models based on real board measurements. In the second step, a simulation framework is developed to evaluate accurately the architectural parameters of the elaborated power models. The proposed methodology has several benefits: it improves significantly the accuracy of the functional level approach and the power consumption estimation can be accomplished without a costly and complex material. In order to speed up the estimation process, our methodology refers to the selection of data pattern size and to the application sampling technique. Experimental results show that our tool achieves high simulation speed of 21 times faster with a marginal power estimation error of 1%.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study 使用RVC技术的FPGA动态重构:逆量化案例研究

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-02 DOI: 10.1109/DASIP.2011.6136863

M. Hentati, Y. Aoudni, J. Nezan, Mohamed Abid, O. Déforges

引用次数: 11

Designing processors using MAsS, a modular and lightweight instruction-level exploration tool 使用MAsS设计处理器，这是一个模块化的轻量级指令级探索工具

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136870

Matthieu Texier, E. Piriou, M. Thévenin, R. David

引用次数: 2

Development of a method for image-based motion estimation of a VTOL-MAV on FPGA 基于FPGA的垂直起降飞行器图像运动估计方法研究

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136880

N. Frietsch, I. Pashkovskiy, G. Trommer, L. Braun, M. Birk, M. Hübner, J. Becker

引用次数: 2

A new approach to 3D form recognition within video capsule endoscopic 视频胶囊内窥镜内三维形态识别的新方法

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136872

J. Ayoub, B. Granado, O. Romain, Y. Mohanna

引用次数: 1

A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods 一种灵活的基于noc的LDPC码解码器实现及带宽降低方法

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136889

C. Condo, G. Masera

{"title":"A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods","authors":"C. Condo, G. Masera","doi":"10.1109/DASIP.2011.6136889","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136889","url":null,"abstract":"The need for efficient and flexible LDPC (Low Density parity Check) code decoders is rising due to the growing number and variety of standards that adopt this kind of error correcting codes in wireless applications. From the implementation point of view, the decoding of LDPC codes implies intensive computation and communication among hardware components. These processing capabilities are usually obtained by allocating a sufficient number of processing elements (PEs) and proper interconnect structures. In this paper, Network on Chip (NoC) concepts are applied to the design of a fully flexible decoder, capable to support any LDPC code with no constraints on code structure. It is shown that NoC based decoders also achieve relevant throughput values, comparable to those obtained by several specialized decoders. Moreover, the paper explores the area and power overhead introduced by the NoC approach. In particular, two methods are proposed to reduce the traffic injected in the network during the decoding process, namely early stopping of iterations and message stopping. These methods are usually adopted to increase throughput. On the contrary, in this paper, we leverage iteration and message stopping to cut the area and power overhead of NoC based decoders. It is shown that, by reducing the traffic injected in the NoC and the number of iterations performed by the decoding algorithm, the decoder can be scaled to lower degrees of parallelism with small losses in terms of BER (Bit Error Rate) performance. VLSI synthesis results on a 130 nm technology show up to 50% area and energy reduction while maintaining an almost constant throughput.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Methodology for designing partially reconfigurable systems using transaction-level modeling 使用事务级建模设计部分可重构系统的方法学

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) Pub Date : 2011-11-01 DOI: 10.1109/DASIP.2011.6136897

François Duhem, F. Muller, P. Lorenzini

引用次数: 9