International Symposium on Code Generation and Optimization (CGO'06)最新文献

Constructing virtual architectures on a tiled processor 在平铺处理器上构造虚拟架构

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.11

D. Wentzlaff, A. Agarwal

{"title":"Constructing virtual architectures on a tiled processor","authors":"D. Wentzlaff, A. Agarwal","doi":"10.1109/CGO.2006.11","DOIUrl":"https://doi.org/10.1109/CGO.2006.11","url":null,"abstract":"As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these resources as individually controllable, parallel processing elements. While such architectures excel at parallel applications, they seldom support legacy single-threaded applications. In this work, we propose using parallel resources to facilitate execution of legacy codes with acceptable performance on parallel architectures containing a drastically different instruction set through the use of an all software parallel dynamic binary translation engine. This engine spatially implements different portions of a superscalar processor across distinct parallel elements thus exploiting the pipeline parallelism inherent in a superscalar. This virtual micro architecture facilitates changing the allocation of silicon resources between different superscalar units in software which is not possible when special purpose physical resources are built. We propose building dynamically reconfigurable architectures that inspect the current virtual machine configuration along with the dynamic instruction stream and change the configuration to best suit the program's needs at runtime. An x86 to Raw parallel translation engine was built in which tiles dedicated to translation can be traded for tiles dedicated to the memory system as an example of dynamic reconfiguration.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117076073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A compiler-guided approach for reducing disk power consumption by exploiting disk access locality 一种编译器引导的方法，通过利用磁盘访问局部性来减少磁盘功耗

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.2

S. Son, Guangyu Chen, M. Kandemir

{"title":"A compiler-guided approach for reducing disk power consumption by exploiting disk access locality","authors":"S. Son, Guangyu Chen, M. Kandemir","doi":"10.1109/CGO.2006.2","DOIUrl":"https://doi.org/10.1109/CGO.2006.2","url":null,"abstract":"Power consumption of large servers and clusters has recently been a popular research topic, since this issue is important from both technical and environmental viewpoints. The prior research proposed disk power management as one of the important ways of reducing overall power of a large system and considered both hardware-based and software-guided disk power reduction schemes. One of the common characteristics of the previously proposed approaches to disk power reduction is that they work with a given disk access pattern. In comparison, the goal of the approach proposed in this paper is to restructure application code using an optimizing compiler so that disk idle periods are lengthened. This in turn allows the underlying disk power management scheme to be more effective since such schemes usually prefer the long idle periods over the short ones. Our approach targets at large scientific applications that operate on disk-resident arrays using nested loops and exhibit regular data access patterns. To test the effectiveness of the proposed approach, we implemented it within an optimizing compiler and performed experiments with six data-intensive applications that manipulate disk-resident data. Our experimental analysis shows that the proposed approach is very successful in practice and reduces the total disk energy consumption on average by 18.17%, as compared to an execution without any disk power management, and by 11.55%, as compared to an execution that employs disks with low-power capabilities without our code restructuring approach.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114748374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Exhaustive optimization phase order space exploration 穷举优化相序空间探索

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.15

P. Kulkarni, D. Whalley, G. Tyson, J. Davidson

{"title":"Exhaustive optimization phase order space exploration","authors":"P. Kulkarni, D. Whalley, G. Tyson, J. Davidson","doi":"10.1109/CGO.2006.15","DOIUrl":"https://doi.org/10.1109/CGO.2006.15","url":null,"abstract":"The phase-ordering problem is a long standing issue for compiler writers. Most optimizing compilers typically have numerous different code-improving phases, many of which can be applied in any order. These phases interact by enabling or disabling opportunities for other optimization phases to be applied. As a result, varying the order of applying optimization phases to a program can produce different code, with potentially significant performance variation amongst them. Complicating this problem further is the fact that there is no universal optimization phase order that will produce the best code, since the best phase order depends on the function being compiled, the compiler, and the target architecture characteristics. Moreover, finding the optimal optimization sequence for even a single function is hard as the space of attempted optimization phase sequences is huge and the interactions between different optimizations are poorly understood. Most previous studies performed to search for the most effective optimization phase sequence assume the optimization phase order search space to be extremely large, and hence consider exhaustive exploration of this space infeasible. In this paper we show that even though the attempted search space is extremely large, with careful and aggressive pruning it is possible to limit the actual search space with no loss of information so that it can be completely evaluated in a matter of minutes or a few hours for most functions. We were able to exhaustively enumerate all the possible function instances that can be produced by different phase orderings performed by our compiler for more than 98% of the functions in our benchmark suite. In this paper we describe the algorithm we used to make exhaustive search of the optimization phase order space possible. We then analyze this space to automatically calculate relationships between different phases. Finally, we show that the results of this analysis can be used to reduce the compilation time for a conventional batch compiler.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117305365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 56

Optimizing dynamic binary translation for SIMD instructions 优化SIMD指令的动态二进制翻译

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.27

Jianhui Li, Qi Zhang, Shu Xu, Bo Huang

引用次数: 30

A cross-architectural interface for code cache manipulation 用于代码缓存操作的跨架构接口

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.3

K. Hazelwood, R. Cohn

{"title":"A cross-architectural interface for code cache manipulation","authors":"K. Hazelwood, R. Cohn","doi":"10.1109/CGO.2006.3","DOIUrl":"https://doi.org/10.1109/CGO.2006.3","url":null,"abstract":"Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentially-altered copy of every instruction that executes, run-time access to a code cache can be a very powerful opportunity. Unfortunately, current research infrastructures lack the ability to model and direct code caching, and as a result, past code cache investigations have required access to the source code of the binary transformation system. This paper presents a code cache-aware interface to the pin dynamic instrumentation system. While a program executes, our interface allows a user to inspect the code cache, receive callbacks when key events occur, and manipulate the code cache contents at will. We demonstrate the utility of this interface on four architectures (IA32, EM64T, IPF, XScale) and present several tools written using our API. These tools include a self-modifying code handler, a two-phase instrumentation analyzer, a code cache visualizer, and custom code cache replacement policies. We also show that tools written using our interface have comparable performance to direct, source-level implementations. Both our interface and sample open-source tools that utilize the interface have been incorporated into the standard distribution of the pin dynamic instrumentation engine, which has been downloaded over 5,000 times in 18 months.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133311490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Post register allocation spill code optimization 后寄存器分配溢出代码优化

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.28

Christopher Lupo, K. Wilken

引用次数: 5

Space-efficient 64-bit Java objects through selective typed virtual addressing 空间高效的64位Java对象通过选择类型的虚拟寻址

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.34

Kris Venstermans, L. Eeckhout, K. D. Bosschere

{"title":"Space-efficient 64-bit Java objects through selective typed virtual addressing","authors":"Kris Venstermans, L. Eeckhout, K. D. Bosschere","doi":"10.1109/CGO.2006.34","DOIUrl":"https://doi.org/10.1109/CGO.2006.34","url":null,"abstract":"Memory performance is an important design issue for contemporary systems given the ever increasing memory gap. This paper proposes a space-efficient Java object model for reducing the memory consumption of 64-bit Java virtual machines. We propose selective typed virtual addressing (STVA) which uses typed virtual addressing (TVA) or implicit typing for reducing the header of 64-bit Java objects. The idea behind TVA is to encode the object's type in the object's virtual address. In other words, all objects of a given type are allocated in a contiguous memory segment. As such, the type information can be removed from the object's header which reduces the number of allocated bytes per object. Whenever type information is needed for the given object, masking is applied to the object's virtual address. Unlike previous work on implicit typing, we apply TVA to a selected number of frequently allocated and/or long-lived object types. This limits the amount of memory fragmentation. We implement STVA in the 64-bit version of the Jikes RVM on an AIX IBM platform and compare its performance against a traditional VM implementation without STVA using a multitude of Java benchmarks. We conclude that STVA reduces memory consumption by on average 15.5% (and up to 39% for some benchmarks). In terms of performance, STVA generally does not affect performance, however for some benchmarks we observe statistically significant performance speedups, up to 24%.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Dynamic class hierarchy mutation 动态类层次突变

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.14

L. Su, Mikko H. Lipasti

{"title":"Dynamic class hierarchy mutation","authors":"L. Su, Mikko H. Lipasti","doi":"10.1109/CGO.2006.14","DOIUrl":"https://doi.org/10.1109/CGO.2006.14","url":null,"abstract":"Class hierarchies in object-oriented programs are used to capture various attributes of the underlying objects they represent, allowing programmers to encapsulate common attributes in base classes while distributing private attributes in lower-level derived classes. In essence, the semantics of the class hierarchy elegantly capture some of the possible states that a particular object can assume. However, class hierarchies are often poorly designed or evolve in ways that fail to fully capture the stateful behavior of objects. This paper proposes an automated approach for detecting stateful class attributes, and then mutating the class hierarchy dynamically to capture such behavior by creating implicit derived classes that can be specialized for specific object states. Our scheme captures both run-time static behavior, which could have been captured by the programmer by restructuring the class hierarchy at the source level; as well as run-time variant behavior, which cannot be captured using source code transformations. In the latter case, objects transition from one state to another and are dynamically mutated from a derived class to a peer derived class corresponding to the object's new state. These class hierarchy mutations create new opportunities for conventional optimizations such as constant propagation, function specialization, and dead code elimination. For our benchmark set, which includes two versions of SPECjbb, we measure speedups of 1.9% to 31.4% within our Jikes-based prototype implementation, with negligible increases in compilation overhead and object code size.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129284282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Software-based transparent and comprehensive control-flow error detection 基于软件的透明和全面的控制流错误检测

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.33

E. Borin, Cheng Wang, Youfeng Wu, G. Araújo

引用次数: 81

Compiler-directed data partitioning for muiticluster processors 多集群处理器的编译器定向数据分区

International Symposium on Code Generation and Optimization (CGO'06) Pub Date : 2006-03-26 DOI: 10.1109/CGO.2006.9

Michael L. Chu, S. Mahlke

{"title":"Compiler-directed data partitioning for muiticluster processors","authors":"Michael L. Chu, S. Mahlke","doi":"10.1109/CGO.2006.9","DOIUrl":"https://doi.org/10.1109/CGO.2006.9","url":null,"abstract":"Multicluster architectures overcome the scaling problem of centralized resources by distributing the datapath, register file, and memory subsystem across multiple clusters connected by a communication network. Traditional compiler partitioning algorithms focus solely on distributing operations across the clusters to maximize instruction-level parallelism. The distribution of data objects is generally ignored. In this work, we examine explicit partitioning of data objects and its affects on operation partitioning. The partitioning of data objects must consider several factors: object size, access frequency/pattern, and dependence patterns between operations that manipulate the objects. This work proposes a compiler-directed approach to synergistically partition both data objects and computation across multiple clusters. First, a global view of the application determines the interaction between data memory objects and their associated computation. Next, data objects are partitioned across multiple clusters with knowledge of the associated computation required by the application. Finally, the resulting distribution of the data objects is relayed to a region-level computation partitioner, which carefully places computation operations in a performance-centric manner.","PeriodicalId":196640,"journal":{"name":"International Symposium on Code Generation and Optimization (CGO'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129702290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21