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A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs 用于开发微程序处理器的计算机辅助设计自动化系统:一种通过HDLs的设计方法
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255310
W. Chen, G. N. Reddy
{"title":"A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs","authors":"W. Chen, G. N. Reddy","doi":"10.1145/255305.255310","DOIUrl":"https://doi.org/10.1145/255305.255310","url":null,"abstract":"This paper presents an approach that provides a total computer aided design environment for developing microprogrammed processors using hardware description languages. This includes the behavioral description, micro-coding, and testing of the integrated microprogrammed processors. To illustrate the design procedure a functionally equivalent micro-coded version of the Motorola's MC6809 processor was modeled, and tested. The results indicate that it is a valid design approach. The micro control unit described through the hardware description language AHPL not only replaces the required microprogram simulator but also emulates its exact hardware. Here the micro control unit and the microcode are emulated and tested as a unit; in much the same way a real processor's micro control unit functions with its stored microcode. The emulated micro-simulator here is used for verifying the MC6809 microcode. It can, however, be used as a general purpose testbed for testing any microcode. The design procedure presented here is for the MC6809 microprogrammed processor, however, the procedure can be used to design any processor with user defined instruction set.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An algorithm for microcode compaction of VHDL behavioral descriptions VHDL行为描述的微码压缩算法
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255313
J. Bhasker
{"title":"An algorithm for microcode compaction of VHDL behavioral descriptions","authors":"J. Bhasker","doi":"10.1145/255305.255313","DOIUrl":"https://doi.org/10.1145/255305.255313","url":null,"abstract":"We present an algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"31 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Extending microcode compaction for real architectures 为实际架构扩展微码压缩
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255312
Mark J. Harris
{"title":"Extending microcode compaction for real architectures","authors":"Mark J. Harris","doi":"10.1145/255305.255312","DOIUrl":"https://doi.org/10.1145/255305.255312","url":null,"abstract":"Microcode compaction is an essential component of any high-level language compiler that generates microcode for a horizontal architecture machine. Recent research into both local and global compaction has assumed the use of a simple abstract machine. Although this assumption simplifies the effort considerably, it neglects addressing and timing problems brought on by the uncommon operation of some machines.\u0000This paper discusses both local and global compaction in terms of the Burroughs D-machine. The D-machine has peculiar timing and an uncommon jump instruction that do not readily fit into proposed compaction algorithms. Methods for handling these problems are presented. In addition, two popular algorithms for performing compaction, list scheduling and trace scheduling, are explained entirely in terms of the D-machine. This should aid the reader in understanding the problem and evaluating any alternatives.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Operation scheduling in reconfigurable, multifunction pipelines 可重构、多功能管道中的作业调度
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255319
Jack S. Walicki, J. Laughlin
{"title":"Operation scheduling in reconfigurable, multifunction pipelines","authors":"Jack S. Walicki, J. Laughlin","doi":"10.1145/255305.255319","DOIUrl":"https://doi.org/10.1145/255305.255319","url":null,"abstract":"One of the key issues in the efficient use of pipelines is the problem of pipeline scheduling. An overview of the research in pipeline scheduling is presented. The scheduling problem for multifunction, dynamically reconfigurable pipelines is studied from the point of view of retargetable microcode compilation. A modified greedy strategy using the criterion of the earliest completion time tc is presented with an example.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133483890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A visual microprogramming system 一个可视化的微程序设计系统
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255309
T. Baba, H. Minakawa, K. Okuda
{"title":"A visual microprogramming system","authors":"T. Baba, H. Minakawa, K. Okuda","doi":"10.1145/255305.255309","DOIUrl":"https://doi.org/10.1145/255305.255309","url":null,"abstract":"A visual microprogramming system has been developed to support all aspects of the microprogramming process for a microprogrammed computer. The user can specify microoperations on a displayed hardware configuration. A graphical microprogram list has also been designed to display several microinstructions on the screen. Optimization may also be done on the screen. A visual simulator graphically illustrates the execution of microoperations on the screen, while allowing the user to control the simulator by using several commands. Preliminary evaluation results are also presented.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115467796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SPAM: a microcode based tool for tracing operating system events 一个基于微码的工具，用于跟踪操作系统事件
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255343
S. Melvin, Y. Patt
{"title":"SPAM: a microcode based tool for tracing operating system events","authors":"S. Melvin, Y. Patt","doi":"10.1145/255305.255343","DOIUrl":"https://doi.org/10.1145/255305.255343","url":null,"abstract":"We have developed a tool called SPAM (for System Performance Analysis using Microcode), based on microcode modifications to a VAX 8600, that traces operating system events as a side-effect to normal execution. This trace of interrupts, exceptions, system calls and context switches can then be processed to analyze operating system behavior for the purpose of debugging, tuning or development. SPAM allows measurements to be made on a fully operating UNIX system with little perturbation (typically less than 10%) and without the need for modifying the kernel.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128629499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Computer architecture simulation using a register transfer language 用寄存器转移语言模拟计算机体系结构
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255311
T. Pittman, L. Bartel
{"title":"Computer architecture simulation using a register transfer language","authors":"T. Pittman, L. Bartel","doi":"10.1145/255305.255311","DOIUrl":"https://doi.org/10.1145/255305.255311","url":null,"abstract":"ASIM (Architecture Simulator) is a hardware description language for describing the hardware of a digital electronic system. The components of an electronic system are described by three primitives: ALU, Selector, and Memory, which are sufficient to describe any piece of digital electronic equipment. ASIM is different from other hardware description languages in that it uses only these three high-level primitives and is not based upon an underlying programming language. To ease the translation of the specification to hardware, ASIM description primitives closely resemble their hardware counterparts, which leads to more compact descriptions than other languages. ASIM is implemented both in an interpreter and a compiler.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126075940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Distributed microprogramming 分布式微程序设计
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255307
P. Lenders
{"title":"Distributed microprogramming","authors":"P. Lenders","doi":"10.1145/255305.255307","DOIUrl":"https://doi.org/10.1145/255305.255307","url":null,"abstract":"This paper proposes the use of the microprogramming technique for synchronizing multiprocessors. The language used is an extension of CSP including the bi-io and the probe statements. We present a self-stabilizing algorithm for the generation of a two-phase clock; this algorithm is a generalization of the Dining Philosophers Problem, where n philosophers access m resources.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the combination of hardware and software concurrency extraction methods 阐述了硬件与软件相结合的并发抽取方法
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255331
A. Uht, C. Polychronopoulos, J. Kolen
{"title":"On the combination of hardware and software concurrency extraction methods","authors":"A. Uht, C. Polychronopoulos, J. Kolen","doi":"10.1145/255305.255331","DOIUrl":"https://doi.org/10.1145/255305.255331","url":null,"abstract":"It has been shown that parallelism is a very promising alternative for enhancing computer performance. Parallelism, however, introduces much complexity to the programming effort. This has lead to the development of automatic concurrency extraction techniques. Prior work has demonstrated that static program restructuring via compiler based techniques provides a large degree of parallelism to the target machine. Purely hardware based extraction techniques (without software preprocessing) have also demonstrated significant (but lesser) degrees of parallelism. This paper considers the performance effects of the combination of both hardware and software techniques. The concurrency extracted from a given set of benchmarks by each technique separately, and together, is determined via simulations and/or analysis. The “common parallelism” extracted by the two methods is thus also considered, using new metrics. The analytic techniques for predicting the performance of specific programs are also described.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130589493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The instruction parsing microarchitecture of the CVAX microprocessor CVAX微处理器的指令解析微体系结构
MICRO 20 Pub Date : 1987-12-01 DOI: 10.1145/255305.255335
D. Archer
{"title":"The instruction parsing microarchitecture of the CVAX microprocessor","authors":"D. Archer","doi":"10.1145/255305.255335","DOIUrl":"https://doi.org/10.1145/255305.255335","url":null,"abstract":"CVAX is a single chip, CMOS VLSI VAX microprocessor. Several microarchitectural innovations helped achieve the desired performance goal of this machine. In particular, the instruction parsing and prefetching mechanism is different from other VAX implementations. This new instruction parsing microarchitecture is discussed in this paper.","PeriodicalId":194206,"journal":{"name":"MICRO 20","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130404565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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