An algorithm for microcode compaction of VHDL behavioral descriptions

We present an algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.