Proceedings of the 2020 on Great Lakes Symposium on VLSI最新文献_第2页

A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design 基于学习的宽电源电压时序预测框架

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406918

Wei Bao, Peng Cao, Hao Cai, Aiguo Bu

引用次数: 6

TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries TUPIM:用于未修改二进制文件的透明和通用内存处理体系结构

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406896

Sheng Xu, Xiaoming Chen, Xuehai Qian, Yinhe Han

引用次数: 4

Power-Efficient Approximate Multiplier Using Adaptive Error Compensation 采用自适应误差补偿的节能近似乘法器

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406913

Zhixi Yang, Honglan Jiang, Xianbin Li, Jun Yang

{"title":"Power-Efficient Approximate Multiplier Using Adaptive Error Compensation","authors":"Zhixi Yang, Honglan Jiang, Xianbin Li, Jun Yang","doi":"10.1145/3386263.3406913","DOIUrl":"https://doi.org/10.1145/3386263.3406913","url":null,"abstract":"In this paper, a design framework is proposed for a power-efficient approximate multiplier using adaptive error compensation and the optimal error compensation values are determined by using probability theory, resulting in a minimal mean-squared-error (MSE). To further pursue the viability of adaptive accuracy, adaptive error compensation scheme using different levels of quantization is utilized for the predetermined compensation values. The simulation results show that the approximate multipliers based on the proposed design framework outperform state-of-the-art designs in both accuracy and circuit measurements. Specifically, with a higher accuracy, the proposed designs save up to 36.84% and 21.61% in power consumption compared to state-of-the-art unsigned and signed approximate $16times16$ multipliers, respectively. In terms of power-delay-product (PDP), the improvements are up to 42.3% and 21.93% for the unsigned and signed multiplier designs, respectively. Finally, the approximate multipliers are further assessed in the implementation of an FIR filter. It shows that the proposed approximate multiplier achieves a similar filtering quality to the accurate design, with more than 50% reduction in power dissipation.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117077461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Session details: Session 1A: Machine Learning and Neuromorphic Accelerator Designs 会议细节:1A:机器学习和神经形态加速器设计

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422937

Tao Liu

引用次数: 0

Towards Self-Aware Systems-on-Chip Through Intelligent Cross-Layer Coordination 通过智能跨层协调实现自我感知的片上系统

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3409105

F. Kurdahi

引用次数: 0

Is It Approximate Computing or Malicious Computing? 是近似计算还是恶意计算?

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3407594

Ye Wang, Jian Dong, Qian Xu, Zhaojun Lu, G. Qu

{"title":"Is It Approximate Computing or Malicious Computing?","authors":"Ye Wang, Jian Dong, Qian Xu, Zhaojun Lu, G. Qu","doi":"10.1145/3386263.3407594","DOIUrl":"https://doi.org/10.1145/3386263.3407594","url":null,"abstract":"Approximate computing (AC) is an attractive energy efficient technique that can be implemented at almost all the design levels including data, algorithm, and hardware. The basic idea behind AC is to deliberately control the trade-off between computation accuracy and energy efficiency. However, with the introduction of AC, traditional computing frameworks are having many potential security vulnerabilities. In this paper, we analyze these vulnerabilities and the associated attacks as well as corresponding countermeasures. More importantly, we propose the vulnerability at data level and demonstrate that without appropriate security mechanism, adversaries can modify the data and convert a secure and trusted AC process to one that produces unexpected errors in the final output. Furthermore, it is difficult to distinguish whether such errors are caused by the approximation nature of AC or from malicious modification and injection. Finally, we propose the information hiding based countermeasures to defend against both existing attacks and the proposed data level attacks, which helps to answer the question: given an error in AC, whether it comes from approximation or it is maliciously introduced.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129946277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique 时序分复用技术的多阶段FPGA路由

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406902

Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo

{"title":"MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique","authors":"Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo","doi":"10.1145/3386263.3406902","DOIUrl":"https://doi.org/10.1145/3386263.3406902","url":null,"abstract":"As the scale of VLSI circuits and fabrication costs increase rapidly, multi-FPGA prototyping systems are widely adopted in industry to make logic verification faster and cheaper. Since routing signals can usually exceed the number of I/O pins in an FPGA, timing division multiplexing (TDM) technique is required to solve this problem. FPGA routing for developing a prototyping system is a big challenge due to the signal delay of TDM. This paper presents MSFRoute, a multi-stage FPGA routing framework for timing division multiplexing technique, to optimize the signal delay and the routability for prototyping systems. In this work, a TDM ratios assignment algorithm with an efficient parallelization method is proposed to optimize inter-FPGA signal delay. Meanwhile, we propose a practical system clock period optimization method to solve critical signal delay problem. Experimental results show that our routing framework reduces TDM ratios by up to 88.3% with an average reduction rate of 41.8%. With the proposed parallelization method, total flow of MSFRoute can get up to 4.38X speedup with a 2.77X speedup on average.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

COCOA: Content-Oriented Configurable Architecture Based on Highly-Adaptive Data Transmission Networks 基于高度自适应数据传输网络的面向内容的可配置体系结构

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406924

Tian Xia, Pengchen Zong, Haoran Zhao, Jianming Tong, Wenzhe Zhao, Nanning Zheng, Pengju Ren

{"title":"COCOA: Content-Oriented Configurable Architecture Based on Highly-Adaptive Data Transmission Networks","authors":"Tian Xia, Pengchen Zong, Haoran Zhao, Jianming Tong, Wenzhe Zhao, Nanning Zheng, Pengju Ren","doi":"10.1145/3386263.3406924","DOIUrl":"https://doi.org/10.1145/3386263.3406924","url":null,"abstract":"In domain of parallel computation, most works focus on optimizing PE organization or memory hierarchy to pursue the maximum efficiency, while the importance of data contents has been overlooked for a long time. Actually for structured data, insights on data contents (i.e. values and locations within a structured form) can greatly benefit the computation performance, as fine-grained data manipulation can be performed. In this paper, we claim that by providing a flexible and adaptive data path, an efficient architecture with capability of fine-grained data manipulation can be built. Specifically, we propose COCOA, a novel content-oriented configurable architecture, which integrates multi-functional data reorganization networks in traditional computing scheme to handle the contents of data during the transmission path, so that they can be processed more efficiently. We evaluate COCOA on various problems: complex matrix algorithm (matrix inversion) and sparse DNN. The results indicates that COCOA is versatile enough to achieve high computation efficiency in both cases.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Session details: Session 9: 3D Circuits and Power Circuits 会议详情:第9部分:3D电路和电源电路

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422958

Mohamad Hammam Alsafrjalani

引用次数: 0

Session details: Session 1B: Emerging Memory-Enabled Computing for Future Electronics 会议详情:1B:面向未来电子产品的新兴内存计算

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422938

Xunzhao Yin

引用次数: 0