Proceedings of the 2020 on Great Lakes Symposium on VLSI最新文献

SERN: Modeling and Analyzing the Soft Error Reliability of Convolutional Neural Networks 卷积神经网络的软误差可靠性建模与分析

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406938

Liqi Ping, Jingweijia Tan, Kaige Yan

{"title":"SERN: Modeling and Analyzing the Soft Error Reliability of Convolutional Neural Networks","authors":"Liqi Ping, Jingweijia Tan, Kaige Yan","doi":"10.1145/3386263.3406938","DOIUrl":"https://doi.org/10.1145/3386263.3406938","url":null,"abstract":"Convolutional Neural Networks (CNNs) are popular in artificial intelligence areas due to their high accuracy. Meanwhile, as manufacturing process technology scales, the probability of soft errors occurrence in computer systems increases, which causes reliability challenges for CNNs. For emerging safety and reliability critical CNN applications, such as autonomous vehicles, soft errors may cause catastrophic consequences. Thus it is important to analyze the vulnerability characteristics of CNNs. A common approach to analyze CNNs' reliability is fault injection, which requires a lot of computation resources and is time consuming. Thus a more efficient method is desired. In this work, we propose an analytical model named SERN to analyze the soft error reliability of CNNs, which requires only a small number of parameters in CNN models. Validation on several common CNN models shows SERN can efficiently and accurately perform soft error reliability analysis for CNNs. We also observe that the reliability of CNNs depend on data types, values, the sign of data and types of layers. Take advantage of these observations, we propose to protect vulnerable bits through ECC and protect error-prone layers through redundancy.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125083897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Session details: Session 3A: 3D Flash Memory and FPGA Designs 会议详情:3A: 3D闪存和FPGA设计

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422941

A. Roohi

引用次数: 0

Session details: Session 7A: Machine-learning based Design Automation 会议详情:7A:基于机器学习的设计自动化

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422951

Xiaoqing Xu

引用次数: 0

Session details: Panel I: Cross-Layer Design of Cyber-Physical Systems: from Circuit to Cloud 分论坛一:网络物理系统的跨层设计:从电路到云

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422954

Wanli Chang

引用次数: 0

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors 调光混合缓存以协助芯片多处理器的温度控制

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406951

Chirag Joshi, P. Das, Ashwini A. Kulkarni, H. Kapoor

{"title":"Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors","authors":"Chirag Joshi, P. Das, Ashwini A. Kulkarni, H. Kapoor","doi":"10.1145/3386263.3406951","DOIUrl":"https://doi.org/10.1145/3386263.3406951","url":null,"abstract":"The continuous rise of on-chip components like cores and caches has brought enormous computing capabilities at the cost of high leakage power and temperature. A recent study has shown a substantial spatial temperature variance in modern large on-chip caches. This high temperature elevates the cooling cost and becomes responsible for the thermal breakdown of the chip. One solution to reduce the leakage is the use of non-volatile memory (NVM) like STT-RAM. Other includes incorporating the concept of dark silicon. In this paper, we amalgamate the idea of using STT-RAM in the last level cache (LLC) and the dark silicon approach to shut down certain cache ways to leverage the benefits from both. We address the downsides like higher access latencies of STT-RAM by the use of hybrid cache (SRAM + STT-RAM) and weak endurance of the STT-RAM by wear leveling. We propose a system to handle three different temperature thresholds (high, medium, and low) by appropriately selecting the type of cache ways to be powered off. The proposed system delivers up to 5.38 K reduction in temperature compared to the baseline, 93% reduction in leakage power with an EDP gain up to 92%.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129417986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Session details: Poster Session II 会议详情:海报会议II

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3422956

Soheil Salehi

引用次数: 0

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor 基于reram的低成本神经网络处理器的架构-精度协同优化

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406954

Segi Lee, Sugil Lee, Jongeun Lee, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong, K. Kwon

引用次数: 5

A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing 基于信噪比预测的精确动态可重构近似计算的背景噪声自适应VAD

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3407589

Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang

引用次数: 3

Deep Neural Network accelerator with Spintronic Memory 带有自旋电子存储器的深度神经网络加速器

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3407646

He Zhang, W. Kang, Youguang Zhang, Weisheng Zhao

{"title":"Deep Neural Network accelerator with Spintronic Memory","authors":"He Zhang, W. Kang, Youguang Zhang, Weisheng Zhao","doi":"10.1145/3386263.3407646","DOIUrl":"https://doi.org/10.1145/3386263.3407646","url":null,"abstract":"Utilizing emerging nonvolatile memories to accelerate deep neural network (DNN) has been considered as one of the promising approaches to solve the bottleneck of data transfer during the multiplication and accumulation (MAC). Among them, spintronic memories show tempting prospect due to their low access power, fast access speed, high density, and relatively mature process. As shown in fig.1, according to the principle to achieve DNN computing, it can be mainly divided into three different technical routes. The first one is an \"analog\" method [1, 2], as shown in fig.1(a). By transforming the digital input signals into multi-level voltage signals, and applying them to different columns of the memory array, the MAC results can be obtained in different columns with current integrator and analog to digital converter (ADC). Besides, the WL drivers can control the pulse width of different rows, to achieve the effect of multi-bit weights. This method can theoretically achieve high energy efficiency and computing speed. However, the variation of magnetic tunnel junction (MTJ) may have influence on the computing accuracy. Besides, the power consumption and area overhead of the ADC are also challenging. The other two methods are in a \"digital\" way, and they realize MAC computing through row-by-row read/write operation. Fig.1(b) shows the second reading-based method [3]. The weights of the neural network are stored in the memory cell. By putting the input signal to the modified sensing amplifier (SA), it can also achieve XOR function, which is the core of binary NN, with the content stored in the memory cell. Nevertheless, the modification to the SA is usually to add extra transistors in the read path, which will increase the bit error rate. Fig.1(c) shows the diagram of the last one, which is based on the \"stateful logic\" [4]. The input data is sent to the modified write driver when the WL receiving weight signals from outside I/O. Based on a unique logic paradigm, it can realize XOR function for BNN within 1 or several memory cells during a write cycle. In this talk, we will review the main research status of DNN accelerators based on spintronic memories. Particularly, our recent work on DNN accelerating will be introduced, which can be implemented with different spintronic memories.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131580940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

HTcatcher: Finite State Machine and Feature Verifcation for Large-scale Neuromorphic Computing Systems 大规模神经形态计算系统的有限状态机和特征验证

Proceedings of the 2020 on Great Lakes Symposium on VLSI Pub Date : 2020-09-07 DOI: 10.1145/3386263.3406955

Guorong He, Chen Dong, Xing Huang, Wenzhong Guo, Ximeng Liu, Tsung-Yi Ho

{"title":"HTcatcher: Finite State Machine and Feature Verifcation for Large-scale Neuromorphic Computing Systems","authors":"Guorong He, Chen Dong, Xing Huang, Wenzhong Guo, Ximeng Liu, Tsung-Yi Ho","doi":"10.1145/3386263.3406955","DOIUrl":"https://doi.org/10.1145/3386263.3406955","url":null,"abstract":"Recent advances in resistive synaptic devices have enabled the emergence of brain-inspired smart chips. These chips can execute complex cognitive tasks in digital signal processing precisely and efficiently using an efficient neuromorphic system. The neuromorphic synapses used in such chips, however, are very sensitive to the external environment, thereby weakening their resistance to malicious modifications such as hardware Trojans and backdoors. Accordingly, in this paper, we propose HTcatcher, a security verification technique for hardware threat detection in neuromorphic computing systems, incorporating finite state machine and feature verification simultaneously, which has never been considered in prior work. Furthermore, we propose a pseudo-random matrix verifying technique for memory optimization, which can reduce the memory overhead of the multi-dimensional features in the system significantly. Experimental results confirm that the proposed method can identify the malicious modifications in the system accurately, while reducing the memory usage by 25%-50%.","PeriodicalId":190751,"journal":{"name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","volume":"755 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3