2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers最新文献_第4页

2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS 2.2 A +70dBm IIP3单端电平衡双工器，0.18um SOI CMOS

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7062851

B. V. Liempd, B. Hershberg, K. Raczkowski, Saneaki Ariumi, U. Karthaus, Karl-Frederik Bink, J. Craninckx

引用次数: 52

26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme 26.2一个5.5fJ/ convstep 6.4MS/S 13b SAR ADC，采用冗余辅助背景错误检测和校正方案

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7063125

M. Ding, P. Harpe, Yao-Hong Liu, B. Busze, K. Philips, H. D. Groot

{"title":"26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme","authors":"M. Ding, P. Harpe, Yao-Hong Liu, B. Busze, K. Philips, H. D. Groot","doi":"10.1109/ISSCC.2015.7063125","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063125","url":null,"abstract":"Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130289335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

5.2 A 110dB SNR ADC with ±30V input common-mode range and 8μV Offset for current sensing applications 5.2 110dB信噪比ADC，输入共模范围为±30V，偏移量为8μV，用于电流传感应用

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7062940

Long Xu, B. Gonen, Qinwen Fan, J. Huijsing, K. Makinwa

引用次数: 28

6.1 A 1/1.7-inch 20Mpixel Back-illuminated stacked CMOS image sensor for new imaging applications 6.1 1/1.7英寸2000万像素背光堆叠CMOS图像传感器，用于新的成像应用

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7062950

A. Suzuki, Nobutaka Shimamura, T. Kainuma, N. Kawazu, Chihiro Okada, Takumi Oka, K. Koiso, A. Masagaki, Yoichi Yagasaki, Shigeru Gonoi, T. Ichikawa, Masatoshi Mizuno, Tatsuya Sugioka, T. Morikawa, Y. Inada, H. Wakabayashi

引用次数: 41

5.1 A 60V auto-zero and chopper operational amplifier with 800kHz interleaved clocks and input bias-current trimming 一个60V自动调零和斩波运算放大器，带有800kHz交错时钟和输入偏置电流微调

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7062939

Y. Kusuda

{"title":"5.1 A 60V auto-zero and chopper operational amplifier with 800kHz interleaved clocks and input bias-current trimming","authors":"Y. Kusuda","doi":"10.1109/ISSCC.2015.7062939","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062939","url":null,"abstract":"Precision operational amplifiers (opamp) with 30V supply operation have been widely used to support industrial, instrumentation, and other applications [1]. Most of them have been realized with BJT or JFET processes [1] to offer voltage noise PSD better than 10nV/√Hz and offset voltage drift better than 1μV/°C. Recently, opamps with similar specifications have become available using CMOS based processes [2-4], which can offer a cheaper wafer price. Auto-zeroing and/or chopping are used as essential techniques to reduce offset voltage drift and 1/f noise associated with CMOS input differential pairs. The switching action of those techniques, however, results in unwanted output ripples and glitches, which requires a post-filter and limits usable signal bandwidth. Increasing the switching frequency can extend the usable signal bandwidth, though it introduces DC errors such as offset voltage drift and input bias current. Maximum offset voltage drift of 0.02μV/°C and an input bias current of 600pA have been achieved [3], although the switching frequency at 60kHz limits the usable signal bandwidth. A high switching frequency of 333kHz has been achieved [2], while the maximum offset voltage drift and input bias current are 0.085μV/°C and 850pA, respectively.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131414511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique 13.8采用中频正交后向散射技术的5.8GHz射频供电收发器，采用113μW 32-QAM发射机

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7063019

A. Shirane, H. Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, N. Ishihara, K. Masu

{"title":"13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique","authors":"A. Shirane, H. Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, N. Ishihara, K. Masu","doi":"10.1109/ISSCC.2015.7063019","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063019","url":null,"abstract":"Although it is obvious that using a trillion sensor nodes for wireless sensor network (WSN) application would deeply exacerbate the spectral congestion issue, RF-powered sensor nodes [1,2] still support only low spectral-efficiency modulation such as OOK. State-of-the-art standard-compliant RF transceivers for low-power applications have been achieving multilevel modulation such as n/8 D8PSK [3], but their power consumption is as large as 1mW without PA even in the 400MHz band because of the large power consumption of the RF synthesizer, which is required to provide high-frequency accuracy and low phase noise for multilevel modulation. This work presents an IF-based quadrature backscattering technique, enabling n-PSK and n-QAM without an RF PLL. The presented technique exploits the passive RFID technologies, but can realize both amplitude and phase modulation concurrently. Our TX in 65nm Si CMOS achieves spectral efficiency of 3.3b/s/Hz with 32QAM while consuming 113uW with a 0.6V power supply in our measurements, which has 6.6 times better spectral efficiency than previous RF-powered wireless transceivers [1,2]. The prototype RF-powered sensor node with our transceiver including the TX, RX, and an RF energy harvester (RF-EH), succeeds in a wireless temperature-sensing application.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128024163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS 10.3一个7.5mW 7.5Gb/s混合NRZ/多音串行数据收发器，用于40nm CMOS的多点存储接口

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7062985

K. Gharibdoust, A. Tajalli, Y. Leblebici

引用次数: 15

22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS 22.3用于28nm FDSOI CMOS自适应153fJ/b光接收器的4至11ghz注入锁定四分之一速率时钟

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7063097

M. Raj, S. Saeedi, A. Emami-Neyestanak

{"title":"22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS","authors":"M. Raj, S. Saeedi, A. Emami-Neyestanak","doi":"10.1109/ISSCC.2015.7063097","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063097","url":null,"abstract":"Modern SoC systems impose stringent requirements on on-chip clock generation and distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the past to provide a low-power, low-area and low-jitter solution. Ring-based injection-locked oscillators (ILO) can also be used to generate quadrature phases from a reference clock without frequency division, which is desirable for half-rate and quarter-rate CDR. However, ILO inherently has a small locking range making it less suitable for wideband applications. In addition, drift in the free-running frequency due to PVT variations may lead to poor jitter performance and locking failures. Adding a PLL to an ILO provides frequency tracking. However, PLL-aided techniques have second-order characteristics that lead to jitter peaking. They also add design complexity and power consumption . We present a frequency-tracking method that exploits the dynamics of IL in a quadrature RO to increase the effective locking range. This quadrature locked loop (QLL) is used to generate accurate clock phases for a 4-channel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains per-bit energy consumption across wide data-rates (16 to 32Gb/s) by adaptive body biasing (BB) in a 28nm FDSOI technology.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133946037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

11.7 A multimodality CMOS sensor array for cell-based assay and drug screening 11.7用于细胞分析和药物筛选的多模态CMOS传感器阵列

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7062999

Jong Seok Park, T. Chi, J. Butts, Tracy A. Hookway, T. McDevitt, Hua Wang

{"title":"11.7 A multimodality CMOS sensor array for cell-based assay and drug screening","authors":"Jong Seok Park, T. Chi, J. Butts, Tracy A. Hookway, T. McDevitt, Hua Wang","doi":"10.1109/ISSCC.2015.7062999","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062999","url":null,"abstract":"Cell-based assays are powerful tools to characterize cell- or tissue-specific physiological behaviors under external biochemical stimuli. External biochemical stimuli trigger endogenous cellular mechanisms that produce a cascade of physiological changes, resulting in easily measurable signals. Cell-based assays are widely used for large-scale drug screening in the pharmaceutical industry, where in vitro cultured cells are used to characterize the potency and toxicity of thousands of chemicals, leading to new drug development. This is particularly relevant in individualized medicine as patient-derived cells can test personalized drug responses. However, most current cell-based assays are conducted on single-modality sensors (electrical or optical only), which cannot capture the complexity of multi-parameter physiological responses. Sequentially transporting cell samples through different sensor platforms results in low throughput and potential abrogation of cell functions, while parallel monitoring of multiple samples with different modalities is subject to cell-to-cell variation even in a homogeneous cell population.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131837365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme 17.3采用双分裂控制辅助方案，VMIN提高280mV的28nm 256kb 6T-SRAM

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI: 10.1109/ISSCC.2015.7063052

Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, C. Shuai, Yen-Yao Wang, H. Yamauchi

{"title":"17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme","authors":"Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, C. Shuai, Yen-Yao Wang, H. Yamauchi","doi":"10.1109/ISSCC.2015.7063052","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063052","url":null,"abstract":"Intelligent wearable devices and the Internet of things (IoT) require on-chip SRAM macros with (1) compact area to reduce costs; (2) single supply voltage (VDD) and low minimum VDD (VDDmin) to reduce power consumption; and (3) sufficient speed to facilitate real-time computing. 6T SRAM is compact, but suffers write failure and half-select (HS) disturbance in read/write cycles at low VDD. Previous studies have sought to improve the write margin (WM)of SRAMs by (a) lowering the cell-VDD (CVDD) voltage (=VDD-ΔVcVVD) [1]-[3] (CVDD-D) at the expense of degradation in cell stability (static noise margin, SNM) for CVDD-HS cells; or (b) using negative-bitline (NBL) voltage (=VSS-VNBL) [1,4-6] for cross-point assist at the expense of increased area and power overhead due to the inclusion of pumping capacitors (CNBL). Wordline (WL) voltage under-drive (WLUD, VWL=VDD-VWLUD) is commonly used in 6T SRAMs [2-5] to improve HS/read SNM during read/write cycles; however, this tends to degrade WM and cell read current (ICELL), resulting in slower read/cycle speeds and necessitating an increase in ΔVCVDD or VNBL (CNBL). The maximum ΔVCVDD is limited by the hold SNM of CVDD-HS cells. Large CNBL results in large area and power overhead, particularly in macros with wide I/O and small amount of column-multiplexing (Y-mux). Thus, HS-SNM tradeoffs in lCELL and WM have not yet been solved for 6T cells, except by adding additional transistors (i.e., 8T to 10T).","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122972375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23