10.3一个7.5mW 7.5Gb/s混合NRZ/多音串行数据收发器，用于40nm CMOS的多点存储接口

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI:10.1109/ISSCC.2015.7062985

K. Gharibdoust, A. Tajalli, Y. Leblebici

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引用次数: 15

摘要

CMOS技术的进步使计算能力呈指数级增长。然而，数据处理的效率还依赖于计算系统中不同单元之间足够的数据通信带宽。内存系统通常采用双列内存模块(dual in-line Memory modules, dimm)，因为它们的容量大，成本低。然而，由于带宽和功率的原因，这些单元和控制器之间的多滴总线(MDB)接口具有挑战性。多音信令在这类接口中具有很好的应用前景[1]。为了满足多路总线对更高带宽不断增长的需求，我们开发了7.5Gb/s (3.75Gb/s/引脚)NRZ/多音(NRZ/MT)收发器，总链路功率效率为1mW/Gb/s。

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10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply dual in-line memory modules (DIMMs) because of their high capacity and low cost. However, the multi-drop bus (MDB) interface between these units and the controller is challenging for bandwidth and power reasons. Multi-tone signaling has promising characteristics for this type of interface [1]. To keep up with the ever growing demand for higher bandwidth in multi-drop buses, we develop a 7.5Gb/s (3.75Gb/s/pin) NRZ/multi-tone (NRZ/MT) transceiver with a total link power efficiency of 1mW/Gb/s.

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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