2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)最新文献

Mastery-Based Learning in Undergraduate Computer Architecture 本科计算机体系结构的掌握型学习

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707147

Ellen Spertus, Zachary Kurmas

{"title":"Mastery-Based Learning in Undergraduate Computer Architecture","authors":"Ellen Spertus, Zachary Kurmas","doi":"10.1109/WCAE53984.2021.9707147","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707147","url":null,"abstract":"Mastery-based learning is an approach in which students are graded based on their demonstrated mastery of explicit learning outcomes rather than by being awarded points less directly connected to course goals. Instead of submitting an assignment only once, students can use feedback to improve their work to increase their learning and grades. We describe our approach to mastery-based grading in introductory computer organization/architecture courses at two different institutions. Specifically, we allowed students to retake tests of basic skills as many times as needed, which was facilitated by programmatically-generated questions. For course projects, students were expected to refine and resubmit projects until they demonstrated mastery by passing all of the provided automated tests. We share our materials and experiences, including the challenge of loosening deadlines to provide students time for continued work without enabling them to fall irretrievably behind.CCS CONCEPTS• Applied computing $rightarrow$ Interactive learning environments; Computer-assisted instruction; • Social and professional topics $rightarrow$ Computer science education; Student assessment; • Computer systems organization $rightarrow$ Architectures. ACM Reference Format:Ellen Spertus and Zachary Kurmas. 2021. Mastery-Based Learning in Undergraduate Computer Architecture. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Interactive Asynchronous Online Computer Architecture Education 交互式异步在线计算机体系结构教育

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707150

Ellen Spertus

引用次数: 0

Digital Teaching an Embedded Systems Course by Using Simulators 利用模拟器进行嵌入式系统课程的数字化教学

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707146

Matthias Koenig, Robin Rasch

引用次数: 0

Improved Processor Design Project Testing 改进的处理器设计项目测试

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707152

Ryan Lund, Connor McMahon, Daniel D. Garcia, B. Nikolić

{"title":"Improved Processor Design Project Testing","authors":"Ryan Lund, Connor McMahon, Daniel D. Garcia, B. Nikolić","doi":"10.1109/WCAE53984.2021.9707152","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707152","url":null,"abstract":"Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley’s fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $rightarrow$ Computer engineering education; •Computer systems organization $rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE ’21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125856969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Framework for Microarchitecture Traces as Abstraction Layer in Computer Architecture Education 微体系结构框架作为计算机体系结构教育的抽象层

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707144

Stefan Wallentowitz

引用次数: 1

Teaching Out-of-Order Processor Design with the RISC-V ISA 用RISC-V ISA教学乱序处理器设计

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707143

Stephen A. Zekany, Jielun Tan, James A. Connolly

{"title":"Teaching Out-of-Order Processor Design with the RISC-V ISA","authors":"Stephen A. Zekany, Jielun Tan, James A. Connolly","doi":"10.1109/WCAE53984.2021.9707143","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707143","url":null,"abstract":"We describe our experience teaching an undergraduate capstone (and elective graduate course) in computer architecture with a semester-long project in which teams of five students design and implement an out-of-order (OoO) pipelined processor core using the open-source RISC-V instruction set. The course content includes OoO scheduling algorithms for instructions to exploit instruction-level parallelism (ILP), example designs, caching, prefetching, and virtual memory. The labs and projects help students gain proficiency with the SystemVerilog language.Students use the concepts learned in class to design processors with the goals of achieving correctness and high performance for a suite of representative test programs. Using RISC-V enables students to validate and benchmark their designs by compiling test programs using GCC with a custom linker. By collaborating as a team, students learn how to write and debug a large code base over the two-month project.For computer architecture educators, we describe technical aspects of the final project and common advanced features implemented by students. We hope describing our experience serves not only to demonstrate a method of teaching modern computer architecture, but also to inspire other course designs centered around other aspects of modern computer architecture (GPUs, FPGAs, hardware/software codesign, etc). We have open-sourced our lab and project materials to enable others to teach similar courses.CCS CONCEPTS• Social and professional topics → Computer engineering education.ACM Reference Format:Stephen A. Zekany, Jielun Tan, James A. Connolly, and Ronald G. Dreslinski. 2021. Teaching Out-of-Order Processor Design with the RISC-V ISA. In ISCA Workshop on Computer Architecture Education (WCAE ’21), June 17, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

PIPS: An Instruction Set Architecture for Teaching Computer Organization 计算机组织教学的指令集体系结构

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707151

Charlie Curtsinger, Jerod J. Weinman

{"title":"PIPS: An Instruction Set Architecture for Teaching Computer Organization","authors":"Charlie Curtsinger, Jerod J. Weinman","doi":"10.1109/WCAE53984.2021.9707151","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707151","url":null,"abstract":"CSC 211: Computer Organization and Architecture at Grinnell College introduces computer science students to the basics of digital circuits, logic design, and computer organization/architecture. This course is designed to help students develop a deeper understanding of how processors function, and how their design can impact the code they write. During the course, students build components like adders, multiplexors, ALUs, and registers with real circuits, and larger components in a digital logic simulator (Logisim). This progression culminates in a four-week lab sequence where students create an assembler and datapath for the PIPS Instruction Set Architecture, which we have designed specifically for this course. In this paper we describe the design and specific learning goals of the PIPS architecture, the four-week lab sequence where students implement a working PIPS assembler and datapath, and our experiences using this lab sequence for the past three years. All student starter materials and instructions for these labs are available at DOI:11084/10426, with solutions and grading infrastructure available to instructors upon request. CCS CONCEPTS • Computer systems organization $rightarrow$ Reduced instruction set computing; • Applied computing $rightarrow$ Education.ACM Reference Format: Charlie Curtsinger and Jerod Weinman. 2021. PIPS: An Instruction Set Architecture for Teaching Computer Organization. In WCAE ’21: Workshop on Computer Architecture Education, June 17, 2021. ACM, New York, NY, USA, 8 pages. https://doi.org/11084/10437","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129892525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future 计算机体系结构的指导机会:分析过去，发展未来

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707614

Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, A. Mahmoud, Saugata Ghose, Joel S. Emer

{"title":"Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future","authors":"Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, A. Mahmoud, Saugata Ghose, Joel S. Emer","doi":"10.1109/WCAE53984.2021.9707614","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707614","url":null,"abstract":"Academic mentoring programming is a powerful tool used for supporting, engaging, and retaining students in their fields of study. Researchers have long known the positive effects of academic mentoring, particularly for students from underrepresented and marginalized backgrounds. The computer architecture community currently hosts an assortment of mentoring programs geared toward women, underrepresented students, junior graduate students, and undergraduates alike.In this work, we describe the current state of mentoring opportunities for students in computer architecture. In addition to summarizing various mentoring programs (e.g., CWWMCA, YArch, and uArch), this work details the organization and feedback from two programs (MaSA and MaSS) that the authors currently run and organize. Based on feedback from these short-term mentoring programs, along with relevant mentoring research literature, we identify opportunities for developing more productive longer-term mentoring programming for the computer architecture community. Following mentoring literature, this work makes a strong case for offering both short-term and long-term mentoring programs in the future; in particular, mentoring literature show the need for time in forming mentoring relationships for mentees to receive the multifaceted benefits of mentoring.ACM Reference Format:Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, and Joel Emer. 2021. Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. In WCAE ’21: Workshop on Computer Architecture Education, June 17,2021, Online. ACM, New York, NY, USA, 9 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Digital Design and RISC-V Computer Architecture Textbook 数字设计与RISC-V计算机体系结构教材

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707615

Sarah L. Harris, D. Harris

{"title":"Digital Design and RISC-V Computer Architecture Textbook","authors":"Sarah L. Harris, D. Harris","doi":"10.1109/WCAE53984.2021.9707615","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707615","url":null,"abstract":"This paper describes the authors’ Digital Design and Computer Architecture: RISC-V Edition textbook. The book presents a unified 1-or 2-semester course on digital design and computer architecture. We have found that learning these topics together clarifies and solidifies understanding of both concepts. The textbook begins by describing digital design concepts and techniques, from number systems, logic gates, and transistor-level gate design to synchronous sequential circuits such as finite state machines and other common digital building blocks. It then builds on these concepts to teach computer architecture and processor design by introducing the RISC-V instruction set architecture (ISA), showing how to design three RISC-V processors with limited instructions, and describing various memory organizations, including caches and virtual memory. The textbook also describes logic design using hardware description languages (HDLs), covering SystemVerilog and VHDL side-by-side. The optional appendices and online chapters introduce the C programming language, embedded system design, and practical aspects of digital design including breadboarding, ASIC design, and transmission lines.CCS CONCEPTS • Architectures • Embedded Systems • Logic","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123105270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ripes: A Visual Computer Architecture Simulator Ripes:一个视觉计算机体系结构模拟器

2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) Pub Date : 2021-06-17 DOI: 10.1109/WCAE53984.2021.9707149

Morten B. Petersen

引用次数: 8