Ripes: A Visual Computer Architecture Simulator

Ripes is a visual computer architecture simulator built around the RISC-V ISA. The main feature of Ripes is its tight integration of a built-in assembler, compiler support, and cache simulator, all centered around a visual microarchitecture simulator. Several microarchitectural models are provided to explore the evolutions of a typical processor pipeline, such as the different iterations of processors when going from a single-cycle model to a classic RISC five-stage pipeline. This paper details the core features of Ripes, the design decisions behind them, as well as thoughts on how Ripes may fit into a larger ecosystem by joining the growing movement around open hardware toolchains. Ripes is an actively maintained open-source project and is at the time of writing used in teaching at various universities, as well as in nonacademic settings.ACM Reference Format:Morten B. Petersen. 2021. Ripes: A Visual Computer Architecture Simulator. In Proceedings of WCAE ’21: IEEE Workshop on Computer Architecture Education (WCAE ’21). ACM, New York, NY, USA, 8 pages.